Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-02-19
2002-04-30
Jankus, Almis R. (Department: 2671)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
Reexamination Certificate
active
06380918
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display and more particularly to a liquid crystal display which prevents miscounting of clock signals entered into a driver circuit such as a segment drive circuit that supplies an image drive voltage to each pixel, thereby eliminating flicker on the screen.
2. Description of the Related Art
A liquid crystal display has a liquid crystal panel which comprises a pair of substrates (liquid crystal substrates), at least one of which is transparent, whose display surface is constructed of an array of fine patterns constituting respective pixels. According to the liquid crystal drive control method, there are two types of liquid crystal displays. One is a passive matrix display using a so-called STN liquid crystal material in which pixels are formed at intersections of a pair of upper and lower stripes of electrodes, and another is an active matrix display in which switching devices such as thin-film transistors are provided for individual pixels.
In the passive matrix type, the liquid crystal panel holds a liquid crystal layer of liquid crystal material between a first substrate having a first electrode group (hereinafter referred to as a segment electrode group) formed in a direction bridging one pair of parallel sides of the substrate forming a rectangular screen, and a second substrate having a second electrode group (hereinafter referred to as a common electrode group) formed in a direction crossing the segment electrode group. The liquid crystal panel also has a first multilayer printed circuit board and a second multilayer printed circuit board. The first multilayer printed circuit board is connected to and applies a pixel drive voltage to the segment electrode group through a plurality of segment drive circuits (or segment drivers), each of which is mounted on a tape carrier pad (or TCP) for every two or more segment electrodes. The second multilayer printed circuit board is connected to and applies a common voltage to the common electrode group through a plurality of common drive circuits (or common drivers), each of which is mounted on the TCP for every two or more common electrodes.
On the second multilayer printed circuit board, drive circuits are mounted thereon. The drive circuit applies an image data voltage to the segment electrodes in response to a line clock signal (line pulse, generally denoted CL
1
), a pixel clock signal (pixel pulse, generally denoted CL
2
), and a frame clock signal (frame pulse, generally denoted CL
3
), all supplied from a host computer side.
The pixel clock signal CL
2
is received in from a controller on the host computer side and then supplied at a predetermined level through a buffer circuit to a clock line. The clock line is wired both on the second multilayer printed circuit board and on the first multilayer printed circuit board. The clock line on the first multilayer printed circuit board is connected in parallel to a plurality of segment drivers parallelly. Each of the segment drivers counts the clock signal and applies the image data voltage to predetermined pixels, when a predetermined count value is reached.
FIG. 1
is a schematic diagram showing a conventional liquid crystal display having a liquid crystal panel and multilayer printed circuit boards arranged in this liquid crystal panel. In this liquid crystal display, the screen area of a liquid crystal panel
3
is divided into an upper half and a lower half, which are scanned in parallel. An upper screen area AR
1
is driven by a plurality of segment drivers
16
A
1
to
16
AN mounted on TCPs
15
A
1
to
15
AN connecting the liquid crystal panel
3
to a segment substrate
1
a.
The segment substrate
1
a
is the first multilayer printed circuit board arranged on the upper side of the panel. A lower screen area AR
2
is driven by a plurality of segment drivers
16
B
1
to
16
BN mounted on TCPs
15
B
1
to
15
BN connecting the liquid crystal panel
3
to a segment substrate
1
b.
The segment substrate
1
b
is the first multilayer printed circuit board arranged on the lower side of the panel.
On a common substrate
2
as the second multilayer printed circuit board, a connector
11
, a buffer circuit
12
and logic control circuits
13
a
,
13
b
are mounted. The buffer circuit
12
divides the pixel clock signal CL
2
, receiving from the controller of the host computer to the connector
11
, into two systems of clock line. As described above, the upper screen area AR
1
is driven by a plurality of segment drivers
16
A
1
to
16
AN arranged on the upper side of the liquid crystal panel and the lower screen area AR
2
is driven by a plurality of segment drivers
16
B
1
, to
16
BN arranged on the lower side. The frame clock signal CL
3
is a signal to determine the start timing of the screen (vertical synchronization signal) and the line clock signal CL
1
is a signal to define the start timing of one horizontal scan (horizontal synchronization signal). Explanations of the operation of these two signals are omitted. Signal lines for the clock signal CL
1
, the pixel clock signal CL
2
, and the frame signal clock CL
3
are generally disposed on both the first multilayer printed circuit board and the second multilayer printed circuit board, and are connected by joiners
14
a
,
14
b
between these printed circuit boards.
FIGS.
2
(
a
) and
2
(
b
) are schematic diagrams showing the configuration of a conventional multilayer printed circuit board on the segment side, with FIG.
2
(
a
) representing a perspective view of an essential portion and FIG.
2
(
b
) representing a cross section of FIG.
2
(
a
) taken along the line
2
B—
2
B.
A segment substrate
1
a
, which is the first multilayer printed circuit board, is arranged on the upper side of the liquid crystal panel
3
as shown in (
a
) and connected to the panel through the TCP
15
A
1
,
15
A
2
, . . .
15
AN mounting the segment drivers
16
A
1
,
16
A
2
, . . .
16
AN.
The liquid crystal display of the aforementioned type is described in, for example, Japanese Patent Laid-Open No. 70601/1985 and Japanese Patent Publication No. 13666/1976.
As shown in FIG.
2
(
b
), the multilayer printed circuit board
1
a
has six to ten layers of laminated wire
17
and the clock signal wire
18
is generally arranged on a layer a large distance away from the TCP (generally the lower layer of the multilayer printed circuit board
1
a
). A solder connecting portion
20
of the TCP (TCP
15
A
1
in the figure) is connected to the pixel clock wire
18
through a through-hole
19
. The wire
18
for the pixel clock signal CL
2
serves as a high-speed clock signal on the lower layer, and the inventors have discovered that a capacitive component (parasitic capacitance) is formed in the through-hole
19
region, causing reflection.
FIG. 3
shows an equivalent circuit of the clock wire and
FIG. 4
shows a waveform of the pixel clock signal CL
2
. C
TCP
in
FIG. 3
represents an input capacitance of TCP
15
A
1
, . . .
15
AN, and C
T
represents a parasitic capacitance of the clock wire. The clock signal CL
2
from the buffer circuit
12
is supplied through the clock wire, and counted by the segment driver
16
A
1
, . . .
6
AN, of each TCP. When the count reaches its predetermined value, each of the segment drivers receives data and applies the pixel voltage to the segment wire.
The aforementioned parasitic capacitance C
T
in the clock wire makes the reflected component (−) so large so that a waveform of the clock signal CL
2
is distorted as shown at R in FIG.
4
. When the counting by the segment driver
16
A
1
, . . .
16
AN is performed at the high-to-low transition of the clock signal waveform, a miscounting is caused by a waveform deformation as shown at R in
FIG. 4
which occurs near a threshold V
TH
Of the high level H and the low level L, resulting in a problem of degraded display quality such as occurrence of flicker on the screen.
SUMMARY OF THE INVENTION
An object of the present invention is to overcome the abov
Anabuki Tohko
Chiba Shinsaku
Takahashi Hiroyuki
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Jankus Almis R.
LandOfFree
Liquid crystal display device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Liquid crystal display device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Liquid crystal display device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2837893