Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2002-01-18
2003-11-11
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S087000, C345S214000
Reexamination Certificate
active
06646629
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display control device which is supplied with video signals and synchronous signals to control a liquid crystal panel to display the information of the video signals thereon, and particularly to a liquid crystal display control device for controlling the display operation of video signals which are not supported by driving circuits of the liquid crystal panel.
2. Description of Related Art
As shown in
FIG. 28
, a general computer outputs a horizontal synchronous signal (HSYNC), a vertical synchronous signal (VSYNC) and video signals (R, G, B) to a CRT (Cathode Ray Tube) display device as a target. In the CRT display device, a scan operation on the CRT is carried out on the basis of the horizontal synchronous signal and the vertical synchronous signal thus input to display the video signals on the screen of the CRT.
There is known a liquid crystal display device to which such horizontal and vertical synchronous signals for CRT are input to display video signals thereon. As shown in
FIG. 29
, this type of liquid crystal display device
22
comprises a controller
22
-
a
and an LCD display unit
22
-
b
. The controller
22
-
a
comprises an A/D converter
23
, a data processing circuit
24
, a PLL (Phase Locked Loop) circuit
25
, an LCD display unit
26
and a buffer
27
as shown in FIG.
30
.
On the basis of the horizontal synchronous signal thus input, the PLL circuit
25
generates a dot clock whose period is coincident with a 1-dot period of the video signal. The A/D converter
23
converts the video signal to video data every dot in accordance with the dot clock. The data processing circuit
24
and the LCD display unit
26
also operates while the dot clock is set as a reference operating clock therefor.
For example, Japanese Laid-open Patent Application No. Hei-7-160222 discloses a liquid crystal display device which is designed to support variation of the dot period of input video signals. In the liquid crystal display device, the PLL circuit is controlled on the basis of the value of video data picked up in accordance with the dot clock to generate a dot clock whose period is coincident with the dot period of the video signal.
SUMMARY OF THE INVENTION
In order to enhance the resolution of display images and reduce the flicker of display of a CRT display device, the speed of video signals and synchronous signals output from a computer have been increased, and it is expected that the speed of these signals will be further increased from this time on.
However, in the conventional liquid crystal display device as described above, the dot clock whose period is coincident with the dot period of the input video signal is used as a reference clock, and the A/D conversion and the data processing are carried out on the video signal on the basis of the reference clock. In order to enable input of high-speed video signals, an A/D converter and a PLL circuit which can operate at high speed and are expensive are needed. Further, the high-speed operation of internal circuits induces such a problem that radiation of high-frequency electromagnetic waves and power consumption are increased.
Therefore, an object of the present invention is to provide a liquid crystal display control device which can perform a series of operations from a pickup operation of video signals to a display driving operation of a display panel at a lower speed while suppressing quality deterioration of display images.
In order to attain the above object, according to the present invention, there is provided a liquid crystal display control device for picking up the first video signal and the first synchronous signal to generate the second video signal and the second synchronous signal with which a dot-matrix type liquid crystal panel displays images thereon, which includes a clock generating circuit for generating, on the basis of the first synchronous signal, a 1
-frequency dot clock whose period is equal to n times the dot period of the first video signal (n represents an integer not less than 2) and whose phase is varied on a dot-period basis every frame period of the first video signal, a data input circuit for picking up the first video signal in accordance with the 1
-frequency dot clock and outputting display data which are digital data, a frame memory in which the display data outputted are stored, and a control circuit for generating the second synchronous signal at a predetermined timing and reading out the display data of one frame stored in the frame memory in synchronism with the synchronous signal to generate the second video signal.
REFERENCES:
patent: 5940136 (1999-08-01), Abe et al.
patent: 6097437 (2000-08-01), Hwang
patent: 6340970 (2002-01-01), Furuhashi et al.
patent: 7-134575 (1995-05-01), None
patent: 7-160222 (1995-06-01), None
patent: 10-23359 (1998-01-01), None
Furuhashi Tsutomu
Konuma Satoshi
Kurihara Hiroshi
Maeda Takeshi
Mori Masashi
Antonelli Terry Stout & Kraus LLP
Dinh Duc Q
Hitachi , Ltd.
Hjerpe Richard
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