Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-06-22
2002-05-21
Wu, Xiao (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S096000, C345S211000
Reexamination Certificate
active
06392625
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display apparatus having a level conversion circuit in which a signal having a low voltage amplitude is converted to a signal having a high voltage amplitude; and, in particular, the invention relates to a level conversion circuit for use in a clock interface and a data interface of a liquid crystal display apparatus using thin-film transistors (TFT Thin-Film Transistor).
A level conversion circuit of the type used in a clock interface and a data interface of a liquid crystal display apparatus is described in, for example JP-A 6-216753 and JP-A 6-283979. In the level conversion circuit shown in these publications, a thin-film transistor, such as a multi-crystallization silicon and a metal-oxide semiconductor (MOS Metal-Oxide Semiconductor) having a mono-crystallization silicon, are employed. In such a level conversion circuit, an input signal having a low voltage amplitude is converted to an output signal having a high voltage amplitude for use in a drive circuit for the liquid crystal display apparatus.
The above-stated input signal has, for example, a voltage amplitude of 5 V or 3.3 V, such as used in a common LSI. Further, the above-stated output signal has, for example, a voltage amplitude of 12 V or 15 V, which corresponds to a power supply voltage of an interior circuit of the level conversion circuit.
As examples this level conversion circuit, there are a differential input type level conversion circuit, which inputs a mutually reverse phase signal, and a single phase input type level conversion circuit, which inputs an independent signal. The differential input type level conversion circuit is used in a comparatively high speed clock interface, and the single phase input type level conversion circuit is used in a data interface.
FIG. 9
shows an example of the differential input type level conversion circuit described in JP-A 6-216753. This level conversion circuit
800
is constituted by a pair of input transistors
811
and
812
, a pair of load transistors
813
and
814
, a pair of constant current power supplies
815
and
816
, and a pair of level shift transistors
817
and
818
.
The respective input transistors
811
and
812
and the respective level shift transistors
817
and
818
are each provided as a N type TFT. The respective load transistors
813
and
814
are each provided as a P type TFT. In the level shift transistors
817
and
818
, a drain electrode and a gate electrode are connected to each other and respective source electrodes are connected to input terminals VIN
1
and VIN
2
. Further, to a connection point of the drain electrode and the gate electrode, the constant current power supplies
815
and
816
and the gate electrodes of the input transistors
811
and
812
are connected.
The respective source electrodes of the input transistors
811
and
812
are connected to ground and the respective drain electrodes of the input transistors
811
and
812
are connected to the respective output terminals VOUT
1
and VOUT
2
. The respective drain electrodes of the load transistors
813
and
814
are connected respectively to output terminals VOUT
1
and VOUT
2
. The respective gate electrodes of the load transistors
813
and
814
are connected respectively to the output terminals VOUT
1
and VOUT
2
. The respective source electrodes of the load transistors
813
and
814
are connected to a power supply VDD.
In the level conversion circuit
800
connected in the above-described manner, the signals which are supplied at the input terminals VIN
1
and VIN
2
have a mutually reverse phase. Herein, the operation state of the level conversion circuit
800
will be explained on the assumption that the voltages which are inputted to the input terminals VIN
1
and VIN
2
are 3.3 V and 0 V, respectively, the voltage of the power supply VDD is 15 V, and a threshold voltage of the respective N type transistors is 2 V.
Since each of the level shift transistors
817
and
818
operates to increase the voltage level at the input terminals VIN
1
and VIN
2
with a threshold voltage, the voltages of 5.3 V and 2 V are applied respectively to the gate electrodes of the input transistors
811
and
812
. As a result, the input transistor
811
presents a conductive state and the input transistor
812
presents a non-conductive state, respectively, and then the voltage of the output terminal VOUT
1
becomes 0 V.
Since this output terminal VOUT
1
is connected to the gate electrode of the load transistor
814
, the load transistor
814
presents a conductive state and then the voltage of the output terminal VOUT
2
becomes 15 V. Further, since the load transistor
814
whose gate electrode is connected to the output terminal VOUT
2
becomes a non-conductive state, then the output terminal VOUT
1
maintains the voltage of 0 V.
Next, from the above-described state, the operation wherein the voltages of the input terminals VIN
1
and VIN
2
change respectively to 0 V and 3.3 V will be explained. When the voltages of the input terminals VIN
1
and VIN
2
change respectively to 0 V and 3.3 V, the input transistor
811
presents the conductive state, but the input transistor
812
presents a non-conductive state, respectively.
At this time, since the load transistor
814
, which is connected to the drain electrode of the input transistor
812
becoming the conductive state, presents the conductive state, when the resistances at the conductive states of the input transistor
812
and the load transistor
814
are expressed by RON
2
and RON
4
, the voltage VOUT
2
of the output terminal VOUT
2
at the time at which the voltage of the input terminal changes is expressed by the following formula 1.
VOUT
2
=RON
2
/(RON
2
+RON
4
)×VDD (1)
As understood from the above-stated formula 1, the voltage of the output terminal VOUT
2
at the time at which the voltage of the input terminal changes is determined by a divided voltage ratio between the resistances RON
2
and RON
4
. With the above stated voltage, the load transistor
813
presents the conductive state and the voltage of the output terminal VOUT
1
changes to 15 V. Since the voltage of the output terminal VOUT
1
changes to 15 V, the resistance of the load transistor
814
increases, and finally the load transistor
814
presents a non-conductive state. As a result, the voltage of the output terminal VOUT
2
becomes 0 V.
Herein, to shorten the time from when the conductive state of the input transistor
812
occurs to the time when the voltage of the output terminal VOUT
2
becomes 0 V, it is necessary to make the voltage of the output terminal VOUT
2
approach 0 V as soon as possible by making the resistance value of the resistor RON
2
small in the formula 1.
On the other hand, in the single phase input type level conversion circuit, one approach is employed using the differential input type level conversion circuit explained above, in which a single signal is inputted to one input terminal and a voltage having ½ of the single phase input amplitude is supplied to the other input terminal; or another approach is employed using the differential input type level conversion circuit explained above, in which a single signal is inputted to one input terminal and the single phase input amplitude is supplied to the other input terminal by reversing the single phase signal.
SUMMARY OF THE INVENTION
When the voltage between the drain electrode and the source electrode is constant, the drain current of a TFT or MOS transistor changes in proportion to a square of the effective gate voltage VE, which is a difference between the gate voltage and the threshold voltage Vth. Since the resistance RON, such as RON
2
and RON
4
, under the above-stated conductive state is in inverse proportion to this drain current, the gate voltage increases abruptly in the vicinity of the threshold voltage Vth.
In the case of the above-described level conversion circuit
800
, the drive condition of the gate voltages of the input transis
Kageyama Hiroshi
Mikami Yoshiro
Ohkubo Tatsuya
Sato Hideo
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Wu Xiao
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