Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-06-04
2001-05-08
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S087000, C345S093000, C345S094000, C345S096000, C345S098000, C345S100000, C345S103000, C345S212000, C345S213000
Reexamination Certificate
active
06229513
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to a liquid crystal display apparatus, and more particularly to techniques which are effectively applied to enhance the resolution of a liquid crystal display panel.
An active matrix type liquid crystal display apparatus, which has an active element (for example, a thin film transistor) for each pixel and drives the active elements for switching, applies pixel electrodes with liquid crystal drive voltages (gradation voltages) through the active elements, so that no cross talk occurs between respective pixels. Since a special driving method is not required for preventing cross talk as is the case of a simple matrix type liquid crystal display apparatus, the active matrix type liquid crystal display provides for a multi-level gradation display.
As one type of the active matrix type liquid crystal display apparatus, there is known a TFT (Thin Film Transistor) based liquid crystal display module which comprises a TFT-based liquid crystal display panel (TFT-LCD); drain drivers disposed above the liquid crystal display panel; gate drivers disposed on one side of the liquid crystal display panel; and an interface unit.
In this TFT-based liquid crystal display module, the interface unit is composed of a display control unit and a power supply circuit. The power supply circuit generates drive voltages for applying to the drain drivers, the gate drivers, and a common electrode of the liquid crystal display panel.
The display control unit, formed of a single semiconductor integrated circuit (LSI), controls and drives the drain drivers and the gate drivers based on display control signals including clock signals, a display timing signal, a horizontal synchronization signal and a vertical synchronization signal, and data for display, all of which are transmitted from a computer side.
Each of the drain drivers latches display data, the amount of which corresponds to the number of output lines, in an input register unit based on a clock signal (D
3
) for latching display data (hereinafter referred to as the “clock signal D
3
”) sent thereto from the display control unit. The drain driver also latches display data latched in the input register unit in a storage latch unit based on a clock signal (D
1
) for output timing control sent from the display control unit, and outputs video voltages corresponding to the respective display data latched in the storage latch unit to associated drain lines D of the liquid crystal display panel.
Each of the gate drivers sequentially conducts a plurality of thin film transistors (TFT) connected to associated gate signal lines G of the liquid crystal display panel for every one horizontal scan period based on a frame start instruction signal sent from the display control unit and a clock signal G
1
in synchronism with the clock signal D
1
.
With the foregoing operations, an image is displayed on the liquid crystal display panel. Such techniques are described, for example, in Japanese Patent Application No. 8-247659 which was published as Japanese Laid-Open Patent Application No. 10-97219.
Conventionally, in liquid crystal display apparatus, a higher resolution has been required for liquid crystal display panels, and to meet the high resolution requirement, the resolution of liquid crystal display panels has been enhanced, for example, from 640×480 pixels in VGA (Video Graphics Array) display mode to 800×600 pixels in SVGA (Super Video Graphics Array) display mode.
In recent years, however, as larger screen sizes have been required for liquid crystal display panels, more enhanced resolutions have been needed for liquid crystal display apparatus, such as 1024×768 pixels in XGA (Extended Graphics Array) display mode, 1280×1024 pixels in SXGA (Super Extended Graphics Array) display mode, and 1600×1200 pixels in UXGA (Ultra Extended Graphics Array) display mode.
With the increasingly enhanced resolution of liquid crystal display panels as mentioned above, a display control unit, drain drivers and gate drivers, associated therewith, are also required to have high speed operation capabilities. Particularly, higher display operation frequencies are strongly needed for a clock signal (D
3
) and display data outputted from the display control unit to the drain drivers.
For example, a liquid crystal display panel having 1024×768 pixels in XGA display mode requires a clock signal (D
3
) at a frequency of 65 MHz and display data at a frequency of 32.5 MHz (one half of 65 MHz).
However, while display data at a frequency of 32.5 MHz may be recognized by the drain drivers, it is difficult for the drain drivers to recognize the clock signal (D
3
) at a frequency of 65 MHz since the clock signal (D
3
) is sent from the display control unit to the drain drivers through a signal line provided on a printed wiring board.
More specifically, a signal line provided on a printed wiring board is equivalent to an open-end distributed constant line. When the clock signal (D
3
) at a frequency of 65 MHz is transmitted through this open-end distributed constant line, the clock signal (D
3
) exhibits significant wave distortion which would cause difficulties in recognizing the clock signal (D
3
) with the drain driver.
On the other hand, in order to prevent other electronic devices from malfunctioning due to electromagnetic interference (EMI) noise radiated by an electronic device, electronic devices are regulated in terms of the amount of radiated electromagnetic waves generated thereby. To comply with this regulation, the liquid crystal display modules are also provided with means as countermeasures for reducing the amount of radiated electromagnetic waves generated thereby (so-called unnecessary radiation countermeasures). In this case, however, as the frequency of a clock signal is higher, it becomes more difficult to take countermeasures for reducing electromagnetic interference noise radiated from a printed wiring board.
As is apparent from the foregoing, conventional liquid crystal display apparatus imply the following problems: difficulties in sending a high frequency clock signal (D
3
) from a display control unit to drain drivers when using a higher resolution liquid crystal display panel which is required with an increase in screen size of a liquid crystal display panel; and difficulties in taking countermeasures for preventing unnecessary radiation, even if a high frequency clock signal (D
3
) could be sent.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide techniques for use in a liquid crystal display apparatus for lowering the frequency of clock signals sent to driving means, using similar driving means to those encountered in conventional liquid crystal display apparatus, without increasing the bus width of a bus line for transmitting display data therethrough.
The above and novel features of the present invention will become apparent from the following detailed description of the preferred embodiments and accompanying drawings.
According to one aspect of the present invention, a liquid crystal display apparatus comprises a liquid crystal display panel having a plurality of pixels formed in a matrix configuration, M driving means (M being a positive integer) for applying a plurality of pixels arranged in a column direction with video voltage based on display data, where M is a positive integer, and display control means for sending inputted display data to the M driving means, and for generating control signals including at least clock signals based on input display control signals inputted thereto and sending the control signals to the M driving means to control and drive the M driving means, wherein the display control means, for lowering the frequency of clock signals sent to the driving means, generates N clock signals (N being a positive integer smaller than M) having the same frequency as and different phases from each other, where N is a positive integer smaller than M, and sends the N clock signals to N driving means groups, each
Igarashi Youichi
Nakano Shuuichi
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Hjerpe Richard
Tran Henry N.
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