Liquid crystal cells – elements and systems – Nominal manufacturing methods or post manufacturing...
Reexamination Certificate
2000-01-04
2003-05-20
Kim, Robert H. (Department: 2871)
Liquid crystal cells, elements and systems
Nominal manufacturing methods or post manufacturing...
C349S043000
Reexamination Certificate
active
06567150
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD), such an active matrix liquid crystal display (AMLCD), and a method of manufacturing the same. More particularly, the present invention relates to an LCD and a method of manufacturing the same that prevents defects formed at end portions of lines, such as pads.
2. Discussion of the Related Art
Among display devices for showing visual images on a screen, cathode ray tube (CRT) display devices, which have been used in general, are nowadays being replaced by thin film type flat panel displays which are thin, light and easily usable at any place. Active research activities have been focusing especially on the development of liquid crystal displays because of their high resolution and fast response time suitable for display of motion picture images.
A liquid crystal display works by using polarization and optical anisotrophy of a liquid crystal. The orientation of liquid crystal molecules is controlled by applying an electromagnetic field to the molecules which are arrayed in one direction and polarized due to their long and thin shape. When controlling the orientation of liquid crystal molecules, transmission of light through the liquid crystal is achieved due to the anisotrophy of the liquid crystal. This principle is applied to a display device. Because active matrix liquid crystal displays (AMLCDs), which have TFTs arranged in a matrix pattern and pixel electrodes connected to the TFTs, provide high quality images and natural colors, they are actively studied. The structure of a conventional liquid crystal display will now be described.
The conventional liquid crystal display comprises two panels, on which various elements are placed, and liquid crystal between the two panels. One panel of the LCD includes elements for reproducing colors, called a color filter panel. The color filter panel has color filters of red (R), green (G) and blue (B) which are sequentially arranged and correspond to pixels formed in a matrix pattern on a transparent substrate. Among these color filters, very thin black matrixes are formed in a lattice pattern. They prevent mixture of colors at the boundaries of the color filters. A common electrode covers the color filters, which functions as one electrode generating an electric field applied to the liquid crystal.
The other panel includes switching elements and bus lines which generate the electric field for driving the liquid crystal. It is called an active panel. The active panel has pixel electrodes which are formed on the transparent substrate. The pixel electrodes are opposite to the common electrode formed on the color filter panel, and functions as the other electrode generating the electric field applied to the liquid crystal. Signal bus lines run along the column direction of the array of the pixel electrodes, and data bus lines run along the row direction of the array of pixel electrodes. At a corner of the pixel electrode, a TFT is formed, which applies electromagnetic field to the pixel electrode. A gate electrode of the TFT is connected with the signal bus line (gate bus line), and a source electrode is connected with the data bus line (source bus line). A drain electrode of the TFT is connected to the pixel electrode. A gate pad and a source pad, which function as terminals receiving external signals, are formed at the end portions of the gate bus line and the source bus line, respectively.
When an external electric signal, which is applied to the gate pad, is sent to the gate electrode through the gate bus line, an electrical picture data, which is applied to the source pad, is sent to the source electrode through the source bus line and to the drain electrode. In the case that the electric signal is not applied to the gate electrode, the electrical picture data, which is applied to the source electrode over the gate electrode, is not sent to the drain electrode. Accordingly, it is decided whether the data signal is applied to the drain electrode by controlling the signal to the gate electrode. Therefore, application of the data signal to the pixel electrode, which is connected to the drain electrode, is artificially controlled. In other words, the TFT functions as a switch driving the pixel electrode.
These two panels are joined with a certain distance (called a “cell gap”), and the liquid crystal is injected therebetween. Finally, polarizing plates are attached to the outer surfaces of the two panels, and thereby the liquid crystal panel of the LCD is completed.
There are various manufacturing methods and structures of the liquid crystal displays. Active research has been carried out in order to improve efficiency of the LCD and to reduce the manufacturing costs. Manufacturing method and structure of the LCD, which are related to the present invention, will now be described with reference to
FIG. 1
, which is a plan view showing the conventional LCD, and to
FIG. 2
, which is a cross-sectional view showing a conventional manufacturing process taken along line I—I of FIG.
1
.
Metal including aluminum is deposited on a transparent glass substrate
1
. A low resistive gate bus line
13
a
and a low resistive gate pad
15
a
are formed by patterning the metal with a first mask The low resistive gate bus line
13
a
has the same shape as the gate bus line, which will be formed later. The low resistive gate pad
15
a
is placed at the end portion of the low resistive gate bus line
13
a
(
FIG. 2
a
).
Metal including chromium, molybdenum, tantalum or antimony is deposited on the entire surface of the substrate. A gate electrode
11
, a gate bus line
13
and a gate pad
15
are formed by patterning the metal with a second mask. The gate bus line
13
covers the low resistive gate bus line
13
a.
The gate bus line
13
covers either the entire surface of the low resistive gate bus line
13
a
or a portion of the low resistive gate bus line
13
a.
The gate electrode
11
branches out from the gate bus line
13
and is placed at a corner of the pixel. The gate pad
15
covers the low resistive gate pad
15
a
as the gate bus line
13
covers the low resistive gate bus line (
FIG. 2
b
).
An inorganic insulating material
17
a
such as silicon oxide or silicon nitride, an intrinsic semiconductor material
33
a
such as an intrinsic amorphous silicon, a doped semiconductor material
35
a
such as a doped amorphous silicon, and a metal
21
a
including chromium are sequentially deposited on the entire surface of the substrate. A source electrode
21
, a drain electrode
31
, a source bus line
23
, and a source pad
25
are formed by patterning the metal
21
a
with a third mask. The source electrode
21
is placed over one side of the gate electrode
11
with the intrinsic semiconductor material
33
a
and the doped semiconductor material
35
a
being sandwiched between the source electrode and the gate electrode. The drain electrode
31
is placed over the other side of the gate electrode
11
. A plurality of source electrodes
23
in a row direction are connected with the source bus line
23
. The source pad
25
is placed at the end portion of the source bus line
23
and is connected to an external image signal terminal (
FIG. 2
c
).
The doped semiconductor material
35
a
is dry-etched to form a doped semiconductor layer
35
by using the source electrode
21
, the source bus line
23
and the drain electrode
31
as a mask. The doped semiconductor layer
35
is in ohmic contact with the source electrode
21
, the source bus line
23
and the drain electrode
31
(
FIG. 2
d
).
A semiconductor layer
33
, which functions as a channel, is formed over the gate electrode
11
by patterning the inorganic insulating material
17
a
and the intrinsic semiconductor material
33
a
with a fourth mask. At this patterning step, the gate pad
15
is fully exposed. The doped semiconductor material
35
a
and the intrinsic semiconductor material
33
a
remain under the source pad
25
(
FIG. 2
e
).
An organic passivation layer
37
is
Akkapeddi P. R.
Kim Robert H.
LG. Philips LCD Co. Ltd.
McKenna Long & Aldridge LLP
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