Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
2000-12-05
2002-11-12
Parker, Kenneth (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C349S187000, C349S040000, C349S139000
Reexamination Certificate
active
06480256
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display device for performing an image display by interposing a liquid crystal between two substrates and a method of manufacturing the same.
2. Description of the Related Art
In
FIG. 9A
, there is shown a plan view of an active matrix type TFT liquid crystal display device utilizing thin film transistors (TFTs) as switching elements and, in
FIG. 9B
, a plan view of a main portion centering around a chamfering area A
2
in an end portion of substrate constituting the liquid crystal display device. In this liquid crystal display device, a liquid crystal material is interposed between a 1st substrate
101
and a 2nd substrate
102
, plural signal wirings
103
and plural scan wirings
104
are formed on the 1st substrate
101
, TFTs and pixel electrodes are connected to positions where the signal wirings
103
intersect the scan wirings
104
, and an image is displayed by means of controlling an orientation of the liquid crystal material by driving the TFTs. A
1
shows a display area.
The 1st substrate
101
is produced with its dimension being made somewhat larger than the 2nd substrate
102
, a connecting terminal portion (general term for signal wiring connecting terminals
105
and scan wiring connecting terminals
106
) is formed in the signal wirings
103
and the scan wirings
104
, which are extended outside the 2nd substrate, and it is connected to an external driving circuit at this connecting terminal portion. In addition, the reference numeral
107
denotes chamfering amount marks formed as marks showing chamfering upper and lower limits when a chamfering work is performed to an end portion at a side, of the 1st substrate
101
, where the connecting terminal portion is formed,
109
an extension wiring extended from the signal wiring
103
or the scan wiring
104
, and
110
a short wiring which is formed in the end portion of the 1st substrate
101
to be chamfered and is electrically connected to the plural extension wirings
109
.
In a cell assembling process for superposing the 1st substrate
101
and the 2nd substrate
102
facing the former and injecting the liquid crystal, in order to orient the liquid crystal material, there is required such a process as rubbing polyimide films (orientation films) applied to the 1st substrate
101
and the 2nd substrate
102
with a cloth, but in this process there is a case that a very strong static electricity is generated, and thus an overvoltage is applied to the scan wirings
104
and the signal wirings
103
, so that a line defect is generated by a deterioration of the TFT on the wirings, and the like. As a countermeasure for preventing such a line defect, there has been known a method in which the short wiring
110
for short-circuiting the signal wirings
103
and the scan wirings
104
is disposed in the vicinity of the substrate end portion and, before a lighting inspection process, the short wiring
110
is excised by a chamfering work of an end face.
However, there is a case that the short wiring
110
generates an elimination badness owing to a dispersion in chamfering amount and the like and, in this case, a short circuit between the adjoining wirings occurs, so that there has been a problem that a display badness such as the line defect and a breakage of an inspection driving circuit occur. Further, reversely, in case where the chamfering amount is set large in order to prevent the elimination badness, there have been problems that it takes a time to perform the chamfering work, so that a cost is increased and, besides, a terminal connecting portion and the like are resected.
Further, on the other hand, since the liquid crystal display device is used in a note type personal computer, a portable terminal and the like, it is strongly demanded to lighten them and narrow their frames. As one means for meeting these demands, there is a method of economizing a chamfering region by reducing the chamfering amount in a panel end. In this case, it is required to improve a chamfering accuracy than former times and, in order to realize an improvement in the chamfering accuracy without incurring a cost, there must be established a method of accurately process-controlling the chamfering amount in a usual manufacturing process.
In order to solve such problems of the elimination badness prevention and the chamfering amount reduction as mentioned above, as disclosed in Japanese Patent Laid-Open No. 278514/1996 Gazette, there has been known a method in which marks showing a chamfered state are formed. As shown in
FIG. 9B
, it is shown that, in this method, patterns of the chamfering amount marks
107
showing the chamfered state are disposed/formed on a position which is a lower limit position of the chamfering amount and shows a necessary minimum limit region, including the short wiring
110
, to be chamfered and a position which is an upper limit position of the chamfering amount and shows a region not to be chamfered, and it is possible to easily prevent the elimination badness of the short wiring
110
and an excessive chamfering amount by means of performing a work while confirming, by visual observation, the mark portions in the chamfering process. Further, it is mentioned about the fact that, by means of controlling the chamfering amount by using the chamfering amount marks
107
, a dispersion of the chamfering amount can be easily and accurately grasped, so that the chamfering accuracy can be improved without a new equipment investment.
However, generally, when forming the chamfering amount marks
107
, in order to avoid adding a new process for forming the chamfering amount marks
107
, a conductive thin film such as mainly Cr and A
1
is used because a thin film layer existing on the 1st substrate
101
is concurrently used. Accordingly, in case where the chamfering amount marks
107
are formed independently of another conductive pattern, a pattern of the chamfering amount marks
107
is electrified by a static electricity generated in a manufacturing process such as cell assembling process, so that there have been such risks that an electric discharge occurs in a later process and thus the chamfering amount marks
107
and patterns of insulation film and conductive film in the vicinity thereof are damaged and, additionally, that a display badness such as the line defect occurs by the fact the scan wirings
104
and the signal wirings
103
, which exist near to the chamfering amount marks
107
, are damaged.
In case of avoiding such electric discharge troubles as mentioned above, although there is considered a countermeasure that the pattern of the chamfering amount marks
107
is made an insulation film, since it is necessary to use an opaque material in order to possess a function as the marks, an insulation material such as silicon nitride used on the 1st substrate
101
cannot be concurrently used, so that a new process for forming the chamfering amount marks
107
becomes necessary, thereby leading to an increase in cost.
SUMMARY OF THE INVENTION
The invention has been achieved in order to solve such problems of the prior art as mentioned above, and its object is to provide a display device capable of reducing its cost, lightening its weight and narrowing its frame by preventing a reduction in process yield owing to the display badness resulting from the static electricity generated in a conductive pattern becoming the chamfering amount marks and by reducing the chamfering amount.
The invention provides a liquid crystal display device in which a liquid crystal is interposed between a 1st substrate and a 2nd substrate, wherein a conductive chamfering amount mark provided on the 1st substrate and used as a mark when chamfering the 1st substrate is constituted by a mark pattern disposed in a reference position consisting of at least any of a center, an upper limit and a lower limit of chamfering on the 1st substrate and a connecting wiring connected to the mark pattern, and the chamfering amount mark is left c
Hirosue Miyuki
Sumi Akinori
Takasaki Ichiro
Kabushiki Kaisha Advanced Display
McDermott & Will & Emery
Parker Kenneth
Rude Timothy L.
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