Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
1999-10-07
2004-06-08
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
C438S700000, C438S706000, C438S745000
Reexamination Certificate
active
06746959
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Filed of the Invention
The present invention relates to a method for manufacturing active matrix liquid crystal displays (“AMLCD”), and to the structure of AMLCDs manufactured by such a method.
2. Discussion of the Related Art
AMLCDs comprise active elements such as thin film transistors (“TFT”) as switching devices for driving and controlling each pixel of the display.
As shown in
FIG. 1A
, in a conventional AMLCD including an array of TFTs, substantially rectangular pixel electrodes
47
are closely arranged in rows and columns on a transparent glass substrate. Gate bus lines (address lines)
13
are respectively formed closely along the rows of the pixel electrodes
47
and source bus lines (data lines)
14
are respectively formed closely along the columns of the pixel electrodes.
Referring to
FIG. 1B
, a plan view showing an enlargement of a single pixel of the AMLCD shown in
FIG. 1A
, gate bus lines
13
having gate electrode extensions
33
are formed on a transparent glass substrate
31
(FIG.
2
A). An insulating layer
35
(
FIG. 2B
) covers the gate bus lines
13
and the gate electrodes
33
, and a plurality of parallel source bus lines
14
are provided on the insulating layer extending perpendicular to gate bus lines
13
. Near each gate bus line
13
and source bus line
14
intersection, a semiconductor layer
37
(
FIG. 2B
) is formed on the insulating layer covering the gate bus lines and the gate electrodes. Spaced source and drain electrodes,
43
a
and
43
b
respectively FIG.
2
D), are formed opposite one another on the semiconductor layer. In this manner, TFTs as active elements are formed.
A manufacturing process of a conventional AMLCD is described below with reference to
FIGS. 2A
to
2
E, showing cross-sectional views taken along a line
2
—
2
of FIG.
A gate electrode
33
(extension of a gate bus line
13
) is formed on a transparent glass substrate
31
by depositing and patterning a first metal layer (FIG.
2
A). A first insulating layer (a gate insulating layer)
35
made of SiN
x
, a semiconductor layer
37
made of a-Si, and a second insulating layer made of SiN
x
are then successively deposited on the entire surface of the substrate.
As shown in
FIG. 2B
, an etch-stopper
40
is formed by patterning the second insulating layer, and an impurity doped semiconductor layer
39
including n
+
a-Si is then deposited over the entire substrate and patterned together with the semiconductor layer
37
(FIG.
2
C).
A second metal layer
43
is next deposited on the entire surface of the substrate, which is then patterned to form a bus line, a source electrode
43
a
branching out from the source bus line, and a drain electrode
43
b
. Next, an exposed portion of the impurity doped semiconductor layer
39
is etched using the source and drain electrodes as masks, as shown in FIG.
2
D.
An insulating passivation layer
45
is then formed by depositing another Si-nitride layer over the first insulating layer and the source and drain electrodes. Then a contact hole is formed by etching the insulating passivation layer
45
. An ITO layer is sputter deposited on the insulating passivation layer
45
. The ITO layer is patterned to form a pixel electrode
47
, which is electrically connected to the drain electrode
43
b
through a contact hole (FIG.
2
E).
This conventional process of manufacturing the TFTs is very complicated. Moreover, it takes a great deal of time to pattern the various layers of the AMLCD because the mask must be aligned precisely, and photo-resists must be coated and developed for each mask step. Further, the manufacturing yield is low.
SUMMARY OF THE INVENTION
The objective of the present invention is to provide a method for manufacturing AMLCDs, in which the number of mask steps is reduced by patterning a second metal layer and a semiconductor layer at the same time. Moreover, source and drain electrodes are formed by etching a portion of the second metal layer together with a portion of an impurity doped semiconductor layer using an insulating passivation layer as a mask.
In particular, the method according to the present invention comprises the following steps. A first metal layer is deposited on a transparent substrate, and gate bus lines and gate electrodes are formed by patterning the first metal layer. A first insulating layer, a semiconductor layer and a second insulating layer are sequentially deposited on the substrate on which the gate bus line and the gate electrode are formed. An etch-stopper is formed by patterning the second insulating layer, and an impurity-doped semiconductor layer is deposited on the etch-stopper and the semiconductor layer. A second metal layer is deposited on the impurity-doped semiconductor layer, and the second metal layer, the impurity-doped semiconductor layer and the semiconductor layer are patterned. An insulating passivation layer is deposited on the patterned second metal layer and the first insulating layer. A contact hole is then formed and a part of the second metal layer on the etch-stopper is exposed by patterning the insulating passivation layer. A transparent conductive layer is deposited on the insulating passivation layer and onto the exposed part of the second metal layer. A pixel electrode is formed by patterning the transparent conductive layer such that the pixel electrode is electrically connected with the second metal layer through a contact hole. Source and drain electrodes are formed by etching a part of the second metal layer and a part of the impurity-doped semiconductor layer, with the insulating passivation layer being used as a mask.
An AMLCD, according to the present invention, comprises a transparent glass substrate, gate bus lines and gate electrodes formed on the transparent glass substrate, a gate insulating layer formed on the transparent glass substrate on which the gate bus lines and the gate electrodes are formed, a semiconductor layer formed on the gate insulating layer, an etch-stopper formed on a portion of the semiconductor layer, an impurity-doped semiconductor layer formed on the semiconductor layer and separated into two parts on the etch-stopper, source and drain electrodes formed on each part of the separated impurity-doped semiconductor layer, respectively, an insulating passivation layer formed on the source and drain electrodes and having a contact hole, and a pixel electrode formed on a portion of the insulating passivation layer, the pixel electrode being electrically connected with the drain electrode through the contact hole.
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Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kunemund Robert
LG Philips LCD Co., Ltd.
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