Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2006-01-03
2006-01-03
Osorio, Ricardo (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S209000
Reexamination Certificate
active
06982693
ABSTRACT:
A liquid crystal display is provided which has low power consumption, and which prevents horizontal stripes from occurring without the circuitry becoming more complex. When the write voltage polarity is inverted every plurality of lines, in the n line where the polarity is inverted, the rise in the drain line waveform dulls due to the charging of the drain line. In the n+1 line, because the drain line has been charged by the writing of the n line, waveform dullness does not occur. A difference between the write states in the two lines causes horizontal stripes. Consequently, the output enable signal is activated at the rise of the clock signal, and the gate line is activated after a predetermined time to start the writing. Therefore, writing is not performed during the period of waveform dullness, and the write state is the same across all scan lines.
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Koga Koichi
Okuzono Noboru
McGinn IP Law Group PLLC
NEC LCD Technologies Ltd.
Osorio Ricardo
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