Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-10-10
2004-11-23
Awad, Amr (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S099000, C348S790000
Reexamination Certificate
active
06822633
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display (hereinafter “LCD”), especially to a driving circuit of LCD and an inverter for supplying voltage to a backlight of LCD.
A display panel of a LCD consists of a lot of pixels arranged into a form of matrix, that is, rows and columns. Each pixel in the display panel includes a switching element, such as a thin film transistor (hereinafter “TFT”), connected to respective gate line and signal line. In addition, a pixel electrode is connected to the TFT. When a TFT is turned ON by an electric signal on the respective gate line, a voltage of the respective signal line is applied to the pixel electrode connected to the TFT. An electric field is applied to liquid crystal substances between the pixel electrode and another electrode (hereinafter “counter electrode”) so that the liquid crystal substances around the electrodes are driven to display an image.
A circuit for giving voltages to the pixel electrodes and an operation of the circuit will be described more in detail. As shown in
FIG. 3
, a clock signal CLK, a horizontal synchronous signal HD, a vertical synchronous signal VD, a data enabling signal DENA for specifying display period, a data signal DATA and the like are input to a timing control circuit
1
as input signals. These input signals are previously in phase, that is, synchronized. The timing control circuit
1
generates a control signal SC for a signal line driving circuit
2
and a control signal GC for a gate line driving circuit
3
from these input signals, and the control signal SC is input to the signal line driving circuit
2
with the data signal DATA and the control signal GC is input to the gate line driving circuit
3
.
Using a voltage VDDA supplied from a DC to DC converter (hereinafter “DC/DC converter”)
5
as a power supply, the signal line drive circuit
2
outputs a signal line voltage VS, which is determined by the data signal DATA and the control signal SC, to each signal line. On the other hand, the gate line drive circuit
3
outputs a gate line voltage VG to each gate line, based on the control signal GC and using voltages VGH and VGL supplied from the DC/DC converter
5
as a power supply.
For the display panel
4
, waveforms of a gate line voltage VG, a signal line voltage VS and a counter electrode voltage VCOM are shown in FIG.
5
. In
FIG. 5
, gate line voltages of the “n”th and “n+1”th gate lines are shown above marked with VGn and VGn+1 respectively, and a signal line voltage VS of the “m”th signal line and a counter electrode voltage VCOM are shown below.
Each TFT in the display panel
4
is in an ON state during the gate line voltage VG applied thereto is at the voltage VGH, thereby the signal line voltage VS is applied to the pixel electrode. Thereafter, by switching the gate line voltage VG from voltage VGH to voltage VGL, the TFT is turned OFF so that the pixel electrode is electrically separated from the signal line and maintains the voltage VS until the TFT is turned ON again. Therefore, a voltage, which has been applied to liquid crystal substances between the pixel and counter electrode during this period of OFF state, is theoretically represented by the voltage difference |VS−VCOM| between the pixel and counter electrode at the point when the TFT turned OFF, that is, a voltage V in FIG.
5
.
However, as shown in
FIG. 5
, there appears switching noise of the DC/DC converter
5
on the signal line voltage VS and the counter electrode voltage VCOM in the prior art LCD. Moreover, the gate line voltage VG, the signal line voltage VS and switching operation of the DC/DC converter
5
are not in phase, that is, not synchronized.
Therefore, as shown in
FIG. 5
, the voltage of |VS−VCOM|=Vn when the gate line voltage VGn of the “n”th gate line becomes VGL to turn the TFT OFF, and the voltage of |VS−VCOM|=Vn+1 when the gate line voltage VGn+1 of the “n+1”th gate line becomes VGL to turn the TFT OFF are different. That is, even if the same signal line voltage VS is applied, a voltage |VS−VCOM| applied to liquid crystal substances varies with each gate line, results in an interference fringes (or beat noise) on the display screen.
Typical LCD comprises a backlight
12
as a light source. The backlight
12
consists of a lamp, such as a cold cathode tube, and inverter for supplying voltage to the lamp by oscillation thereof.
In addition, the inverter comprises dimmer function for adjusting brightness of the backlight. Conventionally, as the dimmer function, PWM dimmer method for changing lamp brightness with varying duty ratio of the inverter output is employed.
An oscillation frequency FQ and dimmer signal BR of the inverter are not synchronized with the gate line voltage VG, the signal line voltage VS and the switching frequency of the DC/DC converter. In
FIG. 6
, waveforms of the signal line voltage VS, the switching frequency of the DC/DC converter, oscillation frequency of the inverter and the VCOM influenced by noise are shown.
As shown in
FIG. 6
, since the signal line voltage VS, the switching frequency of the DC/DC converter and oscillation frequency of the inverter are not in phase, voltage VCOM at the end of the period for gate line selection, i.e. at the point when VGH is switched to VGL, is always changing. Therefore, since the value of |VS−VCOM|=V are not steady in each gate line, there appears interference fringes (or beat noise) on the display so that the display quality is deteriorated.
Further, the voltage VDDA for signal line driving circuit and voltages VGH and VGL for the gate line driving circuit also includes voltage variation. In addition, a dimmer signal of the inverter shall not synchronized with a signal line voltage VS and a switching frequency of the DC/DC converter so that the display quality is deteriorated.
Therefore, an object of the present invention is to obtain high-quality display with preventing the interference fringes on the display screen due to the switching noise of this DC/DC converter.
Another object of the present invention is to obtain high-quality display without interference fringes without being influenced by the inverter frequency and the dimmer signals of the backlight.
SUMMARY OF THE INVENTION
A LCD according to the present invention is characterized in that the switching frequency of the DC/DC converter is synchronized with the control signal supplied from the timing control circuit by using a PLL circuit.
Moreover, a LCD of the present invention is characterized in that the oscillation frequency of the inverter for supplying voltage to a lamp of the backlight, and dimmer signals of PWM dimmer method for carrying out switching operation are synchronized with the control signal supplied from the timing control circuit.
According to the present invention, phases of the switching frequency of the voltage supplied from the DC/DC converter and the control signal supplied from the timing control circuit are synchronized, thereby reducing variation of the voltage of |VS−VCOM| for each gate line, that is, switching noise effectively and preventing interference fringes on the display so that high-quality display is obtained.
Moreover, the oscillation frequency of the inverter for supplying voltage to the lamp and the dimmer signal are in phase with the control signal, thereby enables to reduce the frequency interference to prevent the interference fringes, therefore, high quality image can be displayed.
By carrying out phase matching of all signals in LCD such as control signal, switching frequency of the DC/DC converter, further, oscillation frequency and dimmer signal of inverter, it becomes possible to reduce the noise caused by variation in voltage applied to the display to prevent the interference fringe on the display, so that high-quality image can be obtained.
REFERENCES:
patent: 4958915 (1990-09-01), Okada et al.
patent: 5838294 (1998-
Ikemoto Tetsuya
Oura Hisaharu
Shibata Susumu
Takaoka Hironori
Advanced Display Inc.
Awad Amr
Nelson Alecia D.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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