Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Patent
1995-09-22
1997-09-09
Powell, Mark R.
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
345209, G09G 336
Patent
active
056661320
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) for displaying a gray-scale image, and particularly, to an LCD that displays a gray-scale image according to image data quantized by an analog-to-digital (A-D) converter.
2. Description of the Related Art
Television sets employing LCDs usually have A-D converters to digitize analog image signals. A simple-matrix LCD for displaying dynamic images converts an analog luminance signal into a digital signal and carries out pulse-width modulation on the digital signal. The same technique is applicable to an active matrix LCD employing MIM elements, as disclosed in Japanese Examined Patent Publication No. 63-6855. To reduce costs, the LCD television sets frequently employ low-number-of-bit A-D converters and a dithering technique to provide gradations.
FIG. 7 is a block diagram showing an LCD, according to a prior art, employing the dithering technique. The LCD has a 4-bit A-D converter 906. An image signal 902 is supplied to an analog input terminal AIN of the A-D converter 906, which converts the signal into 4-bit data. The 4-bit data is passed through a data bus 908 and is stored in a memory 910a of a signal electrode driver 910. A multiplexer 904 has a top switch 904a for switching high reference voltages Vt1 and Vt2 from one to another and a bottom switch 904b for switching low reference voltages Vb1 and Vb2 from one to another. The output of the switch 904a is connected to a high-reference-voltage input terminal Vrt of the A-D converter 906, and the output of the switch 904b is connected to a low-reference-voltage input terminal Vrb of the converter. The switches 904a and 904b are interlocked and controlled in response to a clock signal .PHI.1 provided by a controller 916.
The controller 916 provides the A-D converter 906 and driver 910 with a signal group .PHI.2 generated according to a horizontal synchronous signal. The signal group .PHI.2 includes a data sampling clock signal, a shift clock signal used to prepare an address of the memory 910a, a latch clock signal used to transfer data in the driver 910, and a timing signal used to carry out pulse-width modulation. The controller 916 provides a scanning electrode driver 912 with a signal group .PHI.3, which includes vertical scan signals such as a start signal for starting a scan operation and a clock signal for sequentially shifting a select pulse. The driver 910 consists of the memory 910a and a pulse-width modulator 910b. The output terminals of the driver 910 are connected to the signal electrodes of a liquid crystal panel 914, respectively. The output terminals of the driver 912 are connected to the scanning electrodes of the panel 914, respectively.
The memory 910a successively stores 4-bit data for one horizontal scan period and then transfers all stored data to the pulse-width modulator 910b. According to a line at a time scanning method generally used, the A-D converter 906 successively quantizes the image signal 902 for a first horizontal scan period into 4-bit data. The 4-bit data is stored in the memory 910a. In a second horizontal scan period, the 4-bit data for the first horizontal scan period is transferred to the modulator 910b in response to the latch clock signal of the signal group .PHI.2 provided by the controller 916. The modulator 910b carries out pulse-width modulation on the 4-bit data and provides drive signals to the signal electrodes of the panel 914. At this time, the driver 912 provides a select signal to a corresponding scanning electrode. As a result, a LCD driving voltage is applied to each pixel in the selected scan line to display a gradation. In the mean time, the A-D converter 906 successively quantizes the image signal 902 for the second horizontal scan period into 4-bit data, and the 4-bit data is stored in the memory 910a. These processes are repeated to display an image on the panel 914.
A dithering technique of realizing 32 gradations with the 4-bit A-D converter 906 will be explained. The image s
REFERENCES:
patent: 5229761 (1993-07-01), Fase
patent: 5438431 (1995-08-01), Ostromoukhov
Akiyama Takashi
Ochi Isao
Citizen Watch Co. Ltd.
Powell Mark R.
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