Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-02-21
2004-01-27
Saras, Steven (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S087000, C345S098000
Reexamination Certificate
active
06683593
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based on and claims benefit of priority from the prior Japanese Patent Applications No. 2000-044299 filed Feb. 22, 2000 and No. 2000-53914 filed Feb. 29, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) having a matrix of signal and scan lines on a principal plane of a substrate, pixel switching elements formed at the intersections of the signal and scan lines, respectively, and drivers integrally formed on the periphery of the principal plane of the substrate, to supply signal voltages.
2. Description of the Related Art
Recent flat displays, typically LCDs, are thin, light, and low power consumption, and therefore, are used for various appliances. Among LCDs, TFT-LCDs (thin-film transistor LCDs) are active matrix LCDs having pixel matrixes and TFTs serving as pixel switching elements. The TFT-LCDs provide clear images at high resolution that is comparable or superior to that of CRTs, and therefore, are used for applications that need high resolution.
Recent TFT-LCDs have drivers within them, to expand an effective display area on a transparent insulating substrate (hereinafter referred to as “array substrate”) and reduce manufacturing costs. This type of TFT-LCD has a scan driver for supplying scan signals to pixel switching elements through scan lines, and a signal driver for supplying video signals to the pixel switching elements through signal lines. These drivers are integrated on an array substrate on which display pixels are formed. TFT-LCDs now being developed have sample-and-hold (S/H) drivers within them. This type of TFT-LCD employs a timing controller consisting of shift registers, etc., to control the sampling of video signals, signal line capacitors for holding video signals supplied through signal lines, and pixel capacitors (liquid crystal capacitors plus supplemental capacitors) into which the video signals from the signal line capacitors are written.
FIG. 1
shows a typical TFT-LCD that incorporates S/H drivers. The TFT-LCD
100
has a transmission-type LCD panel
110
, a scan driver
120
, and a signal driver
130
. These components are integrated on an array substrate (not shown).
The display panel
110
has a matrix of signal lines S (representing signal lines S
1
, S
2
, and the like that are not shown) and scan lines G (representing scan lines G
1
, G
2
, and the like that are not shown). The signal lines S and the scan lines G intersect each other, and at each intersection, there is a TFT
113
serving as a pixel switching element. The TFT
113
has a source electrode connected to the signal line S and a drain electrode connected to a pixel electrode
114
. The pixel electrode
114
faces a counter electrode
115
with a liquid crystal layer
116
interposing between them to provide liquid crystal capacitance Clc. The liquid crystal layer
116
is in parallel with a supplemental capacitor
117
that provides supplemental capacitance Cs. The liquid crystal capacitance Clc and supplemental capacitance Cs hold a video signal written through a signal line S for a given period. The counter electrode
115
receives a common potential Vcom from a counter electrode driver (not shown).
The scan driver
120
has shift registers (S/Rs)
121
and scan buffers
122
in pairs. In response to a vertical synchronizing signal IN
2
and a vertical clock signal CLK
2
from an external driver (not shown), the scan driver
120
successively provides the scan lines G with scan signals.
The signal driver
130
has shift registers (S/Rs)
131
, analog switch buffers
132
, video buses
133
, and analog switches
134
. The analog switches
134
are connected to the signal lines S, respectively. In response to a horizontal synchronizing signal IN
1
and a horizontal clock signal CLK
1
from the external driver, each shift register
131
provides synchronizing signals to control the analog switches
134
through the buffers
132
and analog switch control lines
135
. As a result, video signals Video
1
to VideoN from the external driver are sampled by the signal lines S at given timing.
In the following explanation, the video buses
133
are classified into as positive and negative video buses P
1
to P
12
and N
1
to N
12
, and the analog switch control lines
135
are referred to as timing signal lines TS
1
to TS
4
.
A peripheral area or frame area
140
is part of the surface area of the array substrate. The frame area
140
includes the scan driver
120
and signal driver
130
and does not include the display panel
110
.
When manufacturing the TFT-LCD
100
, the scan driver
120
and signal driver
130
are integrated on an array substrate, which may be an inexpensive glass substrate, through processes similar to those for the display panel
110
. Therefore, the TFT-LCD
100
is manufacturable at lower costs than a TFT-LCD that employs a TAB technique to form a signal driver and a scan driver.
The TFT-LCD
100
has the scan driver
120
and signal driver
130
on the same array substrate where the display panel
110
is formed. This arrangement enlarges the frame area
140
compared with the TAB-type TFT-LCD. The present market prefers compact displays with large screens. It is required, therefore, to reduce the frame area
140
by reducing the circuit scale of TFTs that form the drivers in the frame area
140
.
The size of an LCD is increasing, and the size of an array substrate is also increasing because each array substrate is required to provide as many panels as possible. A large array substrate involves shrinkage and expansion to increase process variations and deteriorate a positioning accuracy for an exposure unit to 1 &mgr;m or more. It is very difficult, therefore, to further miniaturize the drivers. There is another problem as mentioned below.
FIG. 2
roughly shows the structure of the signal driver
130
of
FIG. 1
formed on an array substrate. The scan driver
120
is not directly related to the present invention, and therefore, is omitted. Among the signal lines S, the signal line S
1
is provided with an n-channel TFT (hereinafter referred to as “n-TFT”) serving as an analog switch SWna, and a p-channel TFT (hereinafter referred to as “p-TFT”) serving as an analog switch SWpa. Similarly, the signal line S
2
is provided with an n-TFT serving as an analog switch SWnb and a p-TFT serving as an analog switch SWpb. The switches SWna and SWpa form an analog switch pair for the signal line S
1
, and the switches SWnb and SWpb form an analog switch pair for the signal line S
2
.
The n-TFT serving as the switch SWna and the p-TFT serving as the switch SWpa are formed side by side in parallel with the signal lines S
1
, S
2
, and the like. The drains (D) of these TFTs are connected to wires whose ends are commonly connected to the signal line S
1
. The source (S) of the n-TFT is connected to wiring that is connected to the video bus P
2
. The source of the p-TFT is connected to wiring that is connected to the video bus P
1
. The n- and p-TFTs serving as the switches SWnb and SWpb are similarly connected.
The gate (G) of the n-TFT serving as the switch SWna is connected to the timing signal line TS
2
, and the gate of the p-TFT serving as the switch SWpa is connected to the timing signal line TS
3
. The gate of the n-TFT serving as the switch SWnb is connected to the timing signal line TS
4
, and the gate of the p-TFT serving as the switch SWpb is connected to the timing signal line TS
1
.
FIGS. 3A and 3B
are plan and sectional views showing the n-TFT serving as the switch SWna and the p-TFT serving as the switch SWpa of FIG.
2
.
FIG. 3A
removes the top of the structure of
FIG. 3B
, i.e., some elements on the counter substrate side, to specifically show contact holes in one manufacturing step. There are a substrate
901
, an active layer
911
, a gate insulating film
906
, an interlayer insulating film
908
, a passivation film
910
, gate electrodes
907
, an
Hanazawa Yasuyuki
Kitani Masakatsu
Miyatake Masaki
Sakurai Hiroyuki
Alphonse Fritz
Kabushiki Kaisha Toshiba
Saras Steven
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