Electrical computers and digital processing systems: multicomput – Computer-to-computer protocol implementing – Computer-to-computer data transfer regulating
Reexamination Certificate
2006-10-31
2006-10-31
Cardone, Jason (Department: 2145)
Electrical computers and digital processing systems: multicomput
Computer-to-computer protocol implementing
Computer-to-computer data transfer regulating
C709S213000, C711S147000, C370S429000, C719S314000
Reexamination Certificate
active
07130916
ABSTRACT:
A method and system for reducing memory accesses by inserting qualifiers in control blocks. In one embodiment, a system comprises a processor configured to process frames of data. The processor may comprise a plurality of buffers configured to store frames of data where each frame of data may be associated with a frame control block. Each frame control block associated with a frame of data may be associated with one or more buffer control blocks. Each control block, e.g., frame control block, buffer control block, may comprise one or more qualifier fields that comprise information unrelated to the current control block. Instead, qualifiers may comprise information related to an another control block. The last frame control block in a queue as well as the last buffer control block associated with a frame control block may comprise fields with no information thereby reducing memory accesses to access information in those fields.
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Calvignac Jean Louis
Heddes Marco C.
Logan Joseph Franklin
Verplanken Fabrice Jean
Cardone Jason
International Business Machines - Corporation
Pollack Melvin H.
Voigt, Jr. Robert A.
Winstead Sechrest & Minick PC
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