Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1999-06-30
2003-12-30
Vincent, David (Department: 2661)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S395700
Reexamination Certificate
active
06671274
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memories in transmission systems. More particularly, the present invention relates to the use of link lists and separate memory divisions to increase the bandwidth of the memories.
BACKGROUND
Developments in router technology have led to system designs that provide a general-purpose connection-oriented transfer mode for a wide range of services. These services include the simultaneous transfer of integrated traffic (data, voice, and video traffic) over network systems. Prior art designs have typically relied on synchronous dynamic random access memories (“SDRAMs”) to temporarily store the integrated traffic transmitted between intermediate nodes of these network systems.
The SDRAMs are typically located in the routers or switches of the network system. Typically, an SDRAM is used to store an incoming data cell until the components of the router have processed the cell for transfer to another router or destination. For example, an asynchronous transfer mode (“ATM”) network transmits ATM cells. Accordingly, an ATM cell may be stored in the SDRAM of a router until the switching circuit of the router determines the destination of the ATM cell. Subsequently, the ATM cell is retrieved from the SDRAM and transmitted to the destination node determined by the switching circuit.
FIG. 1
shows a prior art SDRAM used to store ATM cells. In particular, system
100
includes an SDRAM (
110
) coupled to a controller (control
140
) via line
145
. The storage blocks of SDRAM
110
are addressed by address
120
. Accordingly, address
120
may be used to select a memory address for storing an ATM cell (
135
) received on data
130
. Alternatively, address
120
may be used to specify a memory address to retrieve and ATM cell from SDRAM
110
. The retrieved ATM cell is transferred on data
130
to a switching circuitry (not shown) that places header information on the cell. Subsequently, the header information may be used to route the ATM cell across a network.
For example, in an ATM network that establishes a virtual channel connection (“VCC”) between nodes of the ATM. The VCC typically consists of multiple virtual connections and multiple virtual paths. Specifically, a link of the ATM network includes multiple virtual paths, each virtual path identified by a virtual path identifier (“VPI”). Additionally, a link of the ATM network includes multiple virtual connections, each virtual connection identified by a virtual channel identifier (“VCI”). Accordingly, the switching circuitry may retrieve a cell from SDRAM
110
and attach VPI and VCI header information to the cell prior to transmission over an ATM network.
In an ATM network, cell
135
typically comprises fifty-three bytes of data. Accordingly, data line
130
is 128 bits wide and the storage (i.e., writing) or retrieval (i.e., reading) of cell
135
takes four clock cycles. Thus, system
100
provides a basic system for temporarily storing the cells of a network router in a four clock cycle period.
System
100
, however, results in numerous disadvantages when used in a transmission system that requires multiple read and write operations. System
100
also results in numerous disadvantages when used in a router that requires a high data transmission bandwidth. One disadvantage results from the timing restriction of conventional SDRAMs. Specifically, multiple accesses to the same bank of an SDRAM require a pre-charge (i.e., dead) period between each access. Typically, the pre-charge period may last as long as 10 clock cycles. Another disadvantage results from the operation speed of ATM networks. In particular, during high speed operations (e.g., 2.4 gigabits per second), control
140
may process a large number of cells (both arriving and departing from a switch or a router) in a limited number of clock cycles. The current 128 bit bus implementation of SDRAM
110
, however, places constraints on the data transfer speed of system
100
, thus reducing the processing speed of control
140
. Yet another disadvantage results from the design characteristics of SDRAMs. In particular, during a refresh of an SDRAM, data may not be read or written from the SDRAM. Additionally, the transition between a read and write period of an SDRAM requires a dead period. Thus, the design characteristics of the SDRAMs place constraints on the burst transfer of data between system
100
and a remote system.
SUMMARY AND OBJECTS OF THE INVENTION
It is an object of the invention to provide a memory system that stores both ingress and egress cells in a transmission system with a high speed data bandwidth requirement.
It is another object of the invention to provide a switch that uses an efficient memory system to stores both ingress and egress cells.
It is a further object of the invention to reduce bank conflicts during the storage and retrieval of ingress and egress cells in the memory device of a transmission system.
It is a further object of the invention to provide a memory system in a switch that can process ingress or egress cells during a memory refresh.
A transmission system is described that is operable to store a plurality of transmission cells. The transmission system comprises a first memory coupled to a plurality of signals and a first data bus. The first memory is operable to store a first set of the plurality of transmission cells. The transmission system also comprises a second memory coupled to the plurality of signals and a second data bus. The second memory is operable to store a second set of the plurality of transmission cells. The transmission system further comprises a controller coupled to the first memory device and the second memory device. The controller is operable to maintain a list comprising the available storage blocks in the first memory.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.
REFERENCES:
patent: 5621731 (1997-04-01), Dale et al.
patent: 6000020 (1999-12-01), Chin et al.
patent: 6061351 (2000-05-01), Erimli et al.
patent: 6111880 (2000-08-01), Rusu et al.
patent: 6188690 (2001-02-01), Holden et al.
patent: 6233244 (2001-05-01), Runaldue et al.
patent: 6335935 (2002-01-01), Kadambi et al.
patent: 6349097 (2002-02-01), Smith
patent: 6356557 (2002-03-01), Nichols et al.
patent: 6370138 (2002-04-01), Kim et al.
U.S. patent application Ser. No. 09/316,558, James Ding, et al., filed Jun. 30, 1999.
Ding James
Ginjpalli Hariprasad
Blakely , Sokoloff, Taylor & Zafman LLP
Cisco Technology Inc.
Vincent David
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