Link-layer receiver

Details Link-layer receiver Link-layer receiver

2005-10-11

2005-10-11

Ngo, Ricky (Department: 2663)

Multiplex communications

Channel assignment techniques

Details of circuit or interface for connecting user to the...

C370S469000, C710S056000

Reexamination Certificate

active

06954466

ABSTRACT:
A System Packet Interface (SPI) level 4 receiver groups four consecutive 16 bit control/data words into a single 64 bit word (with a resultant rate of up to 210 MHz). The 64 bit word is processed for storage in a dual memory structure comprising two first-in-first-out (FIFO) memories for storing 64 bit words, wherein the 64 bit word may be stored in one, or both, of the FIFOs. The SPI-4.2 receiver issues commands that control subsequent processing of the 64 bit words (e.g., for alignment) using three types of commands, which are based on the relative temporal position of control words in the received data. Temporally, these commands are characterized as: PRE-COMMANDS, POST-COMMANDS and PRESENT-COMMANDS. A parallel general and selection method (PGSM) is used for FIFO Write Command Generation and for Diagonally Interleaved Parity (DIP-4) checking.

REFERENCES:
patent: 6642865 (2003-11-01), Calvignac et al.
patent: 6668297 (2003-12-01), Karr et al.
patent: 2003/0182613 (2003-09-01), Chu
patent: 2003/0193962 (2003-10-01), Primrose et al.
patent: 2003/0196132 (2003-10-01), Chiang
DiGiuseppe et al., “Virtex-II Platform FPGAs Support System Packet Interface Standards for Optical Network,” Jul. 1, 2001, http://www.xilinx.com/publications/products/v2/v2optical.htm.
System Packet Interface Level 4 (SPI-4) Phase 2: OC-192 System Interface for Physical Link Layer Device, Optical Internetworking Forum, Jan. 2001.

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