Link error monitoring

Excavating

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Details

364550, 3642651, 3642662, 364DIG1, G06F 1100

Patent

active

054597315

ABSTRACT:
In a communication network, an efficient link error monitor is provided that completely relieves the microprocessor of computing the link error rate and comparing it with link error rate thresholds. The link error rate computation and the comparison are performed by the physical layer of a communication station. The physical layer generates an interrupt to the microprocessor only if a threshold is crossed and a microprocessor action may be required. The physical layer includes a number of registers that can be conveniently written by the microprocessor to designate the thresholds and monitor the link errors. The link error rate is estimated using a simple estimator that provides a realistic link error rate estimate even at early stages of operation when few link errors have been detected and when, therefore, little statistical information on the link error rate exists.

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National Semiconductor's Fiber Distributed Data Interface Designer's Guide, No. 103751, 1990 Edition, Santa Clara, Calif.
National Semiconductor's Desktop FDDI Handbook, No. 550137, 1992 Edition, Santa Clara, Calif.
FDDI Physical Layer Protocol (PHY-2), Draft Proposed American National Standard (ANSI), Rev. 5, Jun. 17, 1992.
FDDI Hybrid Ring Control (HRC), Draft Proposed American National Standard (ANSI), Rev. 6.2, Publ. May 28, 1992.

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