Link control state machine for controlling a media access...

Multiplex communications – Communication techniques for information carried in plural...

Reexamination Certificate

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Reexamination Certificate

active

06269104

ABSTRACT:

BACKGROUND
The present invention concerns data transfer over a network and pertains particularly to a link control state machine for controlling a media access controller, a serial physical layer device and a media independent interface physical layer device.
The IEEE 802.3 specification has been created and adopted as a method of sending information between computers and other devices. The IEEE 802.3u specification extended the technology for 100 megabits per second networking.
Within the IEEE 802.3 specification a physical sublayer (PHY) includes a Physical Coding Sublayer (PCS), a Physical Media Access (PMA) sublayer, and a Physical Media Dependent (PMD) sublayer. The PCS defines how data is encoded and decoded as well as how the Carrier Sense (CS) and Collision Detection (CD) functions work. The PCS also defines the interface between higher and lower layers in the protocol specification. The PMA defines the mapping of code bits, generation of a control signal (link_status), generation of control signals to the PCS, and clock recovery. The control signal (link_status) indicates the availability of the PMD. The control signals to the PCS indicate Carrier Sense, Collision Detection and Physical Layer Errors. The PMD defines the signaling method and parameters for the various physical parameters that are necessary to address the link's physical requirements.
The PHY is generally placed on a dedicated integrated circuit (chip). The PHY communicates with a separate media access control (MAC) integrated circuit. The MAC provides an interface to a host system.
Some PHY chips provide connectivity for 10Base2 devices. For example, a PHY chip which provides connectivity to an attachment unit interface (AUI) (for 10Base2 connectivity) is available as part LXT908 from Level One Communications, Inc., having a business address of 9750 Goethe Road, Sacramento, Calif. 95827. PHYs which provide 10Base2 connectivity typically interface with a serial MAC chip.
With the advent of the IEEE 802.3u specification, some PHY chips provide connectivity to 10/100T networks. For example, a PHY chip which provides connectivity to 10/100 megabit networks is available as part LXT970 from Level One Communications, Inc. In order to connect a MAC chip to multiple PHY chips which can provide connectivity to 10/100 megabit networks or other types of media, a media independent interface (MII) bus was created. A PHY chip connected to an MII bus transmits to and receives data from a MAC chip in four bit groupings (nibbles) of data. For more information on construction of an MII bus, see Chapter 22 of the IEEE 802.3u specification
Generally, to provide 10Base2 along with 10/100T connectivity, it is necessary utilize two separate MACs. However Seeq Technology Inc. having a business address of 47200 Bayside Pky, Fremont, Calif. 94538-6567 has designed a specialized 10Base2 PHY which can communicate with a MAC over an MII bus. However, this solution requires the use of a specialized 10Base2 PHY.
SUMMARY OF THE INVENTION
In accordance with the preferred embodiment of the present invention, a link control state machine controls a media access controller (MAC). The MAC is for connection to both a serial physical sublayer (serial PHY) and a media independent interface physical sublayer (MII PHY). In a first state of the link control state machine, the serial PHY is isolated from the MAC and the link status of the MII PHY is checked. In a second state, the MAC performs data transfer using the MII PHY and the serial PHY remains isolated from the MAC. The second state is entered from the first state when the check of the link status shows that a link is established. In a third state, the MII PHY is isolated from the MAC and a test frame is sent using the serial PHY. The third state is entered from the first state when there is a link timeout. In a fourth state, the MAC performs data transfer using the serial PHY. The fourth state is entered from the third state when the test frame was transmitted successfully.
In the preferred embodiment, when the link control state machine is in the first state, the serial PHY is isolated from the MAC, the MII PHY is selected, auto-negotiation is enabled and a timeout timer is started. Also, when the link control state machine is in the second state, the link status of the MII PHY is monitored.
Also in the preferred embodiment, when the link control state machine is in the second state and there is a link loss, the link control state machine transitions to the third state. When the link control state machine is in the third state, after the test frame is sent, status of the test frame is checked.
When the link monitor is in the third state, if there is a transmit error indicated by the status of the test frame, the link control state machine transitions to the first state. When the link control state machine is in the fourth state, link status of the MII PHY is checked. If a link is established by the MII PHY, the link control state machine transitions to the first state.
The present invention reduces the cost of providing for simultaneous support of 10BaseT, 100BaseT and 10 base 2 connectivity. A single network card with only one MAC chip can be designed to provide all three connection options. Any MII compatible PHY can be connected simultaneously with any serial PHY. By connecting two PHY chips to a single MAC chip, it is possible to save space and a printed circuit board, and to conserve power consumption. Since the present invention allows compatibility with any serial PHY, the present invention allows the use of any competitively priced 10Base2 PHY.


REFERENCES:
patent: 5784573 (1998-07-01), Szczepanek et al.
patent: 5991303 (1999-11-01), Mills
patent: 6047001 (2000-04-01), Kuo e tal.
patent: 6055241 (2000-04-01), Raza et al.
patent: 6061362 (2000-05-01), Muller et al.
patent: 6067585 (2000-05-01), Hoang
IEEE Standard 802.3u, 1995, Chapter 22 (pp. 27-80), 1995.
Preliminary Data Sheet, 8501/8502 Ethernet MII to AUI Interface Adapter, Seeq Technology, Inc. Jul. 14, 1997, pp. 1-56.

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