Linerless shallow trench isolation method

Details Linerless shallow trench isolation method Linerless shallow trench isolation method

2002-01-18

2003-03-18

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

Reexamination Certificate

active

06534379

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device comprising trench isolation. The invention has particular applicability in manufacturing high density semiconductor devices with submicron design features and active islands isolated by shallow insulated trenches.
BACKGROUND ART
Current demands for high density and performance associated with ultra large scale integration (ULSI) require submicron features of significantly less than 0.25 microns, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity.
Conventional semiconductor devices comprise a substrate and various electrically isolated regions or islands, called active regions, active islands or, simply, islands, in which individual circuit components are formed. The electrical isolation of these active islands is typically accomplished by thermal oxidation of the semiconductor substrate, typically monocrystalline silicon, bounding the active islands. This type of isolation has been referred to as local oxidation of silicon, or LOCOS.
In an effort to enable the further reduction of the size of semiconductor devices, and to enable continued enhancement of transistor and product performance, semiconductor-on-insulator (SOI) wafers increasingly have been used in very-large scale integration (VLSI) or ULSI of semiconductor devices. An SOI wafer typically has a thin layer of silicon on top of a layer of an insulator material. In SOI technology, the semiconductor device is formed entirely in and on the thin layer of silicon, and is isolated from the lower portion of the wafer by the layer of insulator material. In an SOI integrated circuit, essentially complete device isolation may be achieved using conventional device processing methods by surrounding each device, including the bottom of the device, with an insulator. One advantage which SOI wafers have over bulk silicon wafers is that the area required for isolation between devices on an SOI wafer is less than the area typically required for isolation on a bulk silicon wafer.
A type of isolation structure is known as trench isolation, wherein shallow isolation trenches are etched in the substrate between the sites of semiconductor devices and an oxide liner is thermally grown on the trench walls. The trench is then refilled with an insulating material. The resulting structure is referred to as a shallow trench isolation (STI) structure. STI has been widely applied to VLSI and ULSI semiconductor devices, and has been applied recently to SOI integrated circuits for such devices.
Trench isolation has several limitations, which may be exacerbated in SOI devices. One problem is that sharp corners at the top of the trench can result in gate and/or source-drain junction leakage currents and degradation of long-term gate oxide reliability metrics (e.g., voltage-ramp dielectric breakdown (VRDB)). More specifically, such sharp corners may cause unwanted increases in the sub-threshold currents in the channel regions along the edge of the device areas when the FETs are switched on. The device threshold voltage can also be lowered. In order to avoid these problems, it has been found desirable to round the corners of such trenches to increase the radius of curvature and thereby decrease the electric field at the corners. This has been accomplished by, for example, oxidizing the entire inner surface of the newly formed trench, taking advantage of the fact that an exposed corner of a silicon layer etches faster than a flat surface of the silicon layer, thus forming a rounded upper corner at the top of the trench.
However, with SOI devices, the corner rounding solution leads to a new problem. The problem in SOI devices arises as a result of the proximity of the dielectric insulation layer below the silicon active layer. In SOI devices, the shallow isolation trench is etched through the silicon layer to the insulation layer. When the exposed portion of the silicon on the sidewalls of the newly formed trench is oxidized during the process of rounding the corners, a wedge or “bird's beak” of new oxide may form on the underside of the silicon active layer adjacent the isolation trench, between the silicon active layer and the underlying layer of insulating material of the SOI wafer. Thus, as the oxide grows on the sidewalls of the trench, it may grow laterally between the lower edge of the silicon active layer and the underlying oxide insulation layer. In essence, during the process of oxidation which is intended to round the upper corner of the silicon active layer, the lower corner of the silicon active layer is also rounded, forming the “bird's beak” between the silicon active layer and the underlying oxide insulation layer. The problem results when growth of the “bird's beak” creates defects in the silicon crystal structure and/or lifts the silicon layer, due to the pressure of the growing oxide. The defects in the crystal structure may change the electrical characteristics of the semiconductor. The lifting of the silicon layer distorts the surface of the semiconductor device from its desired planarity to an undesirable non-planar condition. As semiconductor device dimensions continue to become smaller, problems such as these both occur more easily and become less tolerable.
Thus, there exists a need for STI methodology applicable to SOI semiconductor devices wherein the problems resulting from sharp corners can be alleviated without creating the problems resulting from “bird's beak” on the underside of the silicon active layer adjacent the isolation trench.
SUMMARY OF THE INVENTION
The present invention provides a method of avoiding formation of the “bird's beak” under the silicon active island while providing rounded upper corners on the silicon active layer in shallow trench isolation of SOI semiconductor devices.
In one embodiment, the present invention relates to a method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of: providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric isolation layer and the dielectric isolation layer is formed on the silicon substrate; forming an isolation trench, the isolation trench defining an active island in the silicon active layer; rounding at least one corner in the active island by application of a high RF bias power high density plasma; and filling the isolation trench with a dielectric trench isolation material by application of a low RF bias power high density plasma.
In another embodiment, the present invention relates to a method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric isolation layer and the dielectric isolation layer is formed on the silicon substrate; forming an isolation trench by etching through the silicon active layer, the isolation trench defining an active island in the silicon active layer; rounding at least one upper corner in the active island by application of a high RF bias power high density plasma, under etching conditions; and filling the isolation trench with a dielectric trench isolation material by application of a low RF bias power high density plasma, under deposition conditions.
The present invention further relates to a silicon-on-insulator semiconductor device, comprising a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric isolation layer and the dielectric isolation layer is formed on the silicon substrate; an isol

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