Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
1999-07-13
2001-01-09
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S155000, C341S156000, C341S158000, C341S159000, C327S563000, C330S252000
Reexamination Certificate
active
06172636
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to analog-to-digital converters (ADCs) and more particularly to folding amplifiers.
2. Description of the Related Art
Single-bit ADCs quantize an analog input signal to a digital output signal that consists of one binary bit. Although useful in themselves, they also serve as building blocks for constructing more complex ADC structures (e.g., serial ADCs and subranging ADCs) in which they are typically positioned in a serial arrangement of ADC stages. The terminal ADC in such an arrangement can generally be a simple comparator but preceding stages must process an input analog signal and pass it to successive stages for further quantization.
An exemplary preceding single-bit stage comprises an amplifier, a subtracter and a comparator that drives a single-bit digital-to-analog converter (DAC) in the form of a switch. The amplifier and the comparator are coupled to the analog input signal and the output of the single-bit DAC is subtracted from the amplifier's output to produce an analog residue signal that is passed to a successive ADC stage.
For one polarity of the input signal, the residue signal equals the amplified input signal less a first analog signal (e.g., a voltage at the upper end of the input signal range) from the DAC. For the other polarity of the input signal, the residue signal equals the amplified input signal less a second analog signal (e.g., a voltage at the lower end of the input signal range) from the DAC.
Accordingly, the residue signal contains two linear regions separated by a discontinuity that occurs at the input signal's polarity transition and equals the difference between the first and second analog signals. In order to maintain a constant signal range between the input and output, the gain of the amplifier is typically configured with a gain of two. Successful operation of a serial arrangement of these single-bit stages, however, is significantly degraded by transients that are generated by each stage's discontinuity.
The discontinuity is avoided by substitution of folding amplifiers which have a positive gain for one polarity of input signal and a negative gain for the other polarity with the output signal generally level-shifted to facilitate signal quantization in a successive folding amplifier. Folding amplifiers have typically been designed in unity-gain and adjustable-gain configurations.
An exemplary adjustable-gain folding amplifier is disclosed in U.S. Pat. No. 5,684,419 issued Nov. 4, 1997 to Frank Murden, et al., and assigned to Analog Devices, Inc., the assignee of the present invention. This amplifier includes first and second differential pairs of transistors that have control terminals complimentarily and differentially coupled to an input differential pair and associated degeneration input resistor and that have current terminals cross-coupled to generate output signals across output resistors. The signal gain can be adjusted by appropriate selection of input and output resistors.
Although adjustable-gain folding amplifiers are generally slower, more complex and less efficient than unity-gain folding amplifiers (e.g., as exemplified by U.S. Pat. No. 5,550,492 issued Aug. 27, 1996 to Frank Murden and assigned to Analog Devices, Inc.), they are especially suited for use as one or more initial stages in N-stage serial ADC arrangements. In these initial stages, their signal gain insures that the input signal range of successive unity-gain folding amplifiers remains above a level that is considered adequate for reliable quantization. This reliability, however, is degraded by any nonlinearity in the transfer functions of the initial stages.
Although presently available adjustable-gain folding amplifiers can be configured to realize various signal gains, they typically exhibit signal nonlinearities that limit the number N of subsequent serially-arranged ADC stages. Because they also typically exhibit gain variations from production unit to unit that can also degrade the performance of subsequent ADC stages, their adjustable gains have generally been limited to small values (e.g., a gain of 2).
SUMMARY OF THE INVENTION
The present invention is directed to linearizing structures and methods for adjustable-gain folding amplifiers. Because these structures and methods linearize and stabilize their gain, adjustable-gain folding amplifiers of the invention improve the performance of subsequent folding amplifier stages, increase the number of allowed subsequent stages and replace the functions of other portions of compound ADCs (e.g., subranging ADCs).
These goals are achieved with the following process steps that generate a folded and level-shifted differential output voltage in linear response to a differential input voltage:
a) with circuit components that include active components, converting the differential input voltage to a signal current;
b) diverting substantially all of the signal current from the active components to flow differentially through first and second current paths;
c) steering currents on the first and second current paths to third and fourth current paths respectively when the input signal has one polarity and to the fourth and third current paths respectively when the input signal has a different polarity;
d) converting currents on the third and fourth current paths to a differential signal voltage; and
e) shifting voltage levels of the differential signal voltage to thereby generate the differential output voltage.
In a method embodiment, the diverting step includes the steps of receiving differential currents from the active components, amplifying the differential currents with a current gain to realize amplified differential currents, and directing the amplified differential currents differentially along the first and second current paths.
In a structural embodiment, the active components include an input differential pair of transistors, the circuit components also include a resistor coupled between the first current terminals of the input differential pair, and a current-feedback circuit receives a differential sense current from second current terminals of the input differential pair, amplifies the differential sense current to a differential feedback current and couples the differential feedback current to the first current terminals of the input pair.
The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings.
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Kester, Walt, et al.,High Speed Design Techniques, Analog Devices, Inc., Norwood, MA., 1996, pp. 4-36 to 4-47.
Elliott Michael R.
Murden Frank
Analog Devices Inc.
Koppel & Jacobs
Tan Vibol
Tokar Michael
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