Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2002-10-23
2003-09-30
Nguyen, Patricia (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S251000, C330S009000, C327S097000, C341S155000
Reexamination Certificate
active
06628167
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to an analog-to-digital converter, and more particularly to a folding amplifier circuit for an analog-to-digital converter.
BACKGROUND ART
Analog-to-digital converters are commonly used in aerospace and other applications. In aerospace applications, in particular, it is typically desirable to reduce power consumption and weight of the various components. Such weight and power reductions reduce the amount of fuel required for the particular aerospace application.
Folding amplifiers used for analog-to-digital converters are known. The output of folding amplifiers when used for an analog-to-digital converter must be linearized. Traditional methods for linearizing such a circuit use an additional pre-distortion or post-distortion stage. U.S. Pat. No. 4,599,602 describes a folding amplifier and serial analog-to-digital architecture. A linearization technique is used that requires a high supply voltage due to the additional voltage required by additional diodes used in the linearization. As a result an increased sized power supply must be provided.
Folding converters utilizing a parallel folding scheme typically require up to 2
n
parallel folding amplifiers for an n-bit converter. Thus, for a 6-bit converter 64 folding amplifiers may be required. Such a design may be simplified by combining lower order folding cells with an interpolation circuit to obtain the remaining quantization levels. However, interpolation often requires an additional encoding circuit which can increase the complexity of the circuit.
A serial folding mechanism is also known. One such serial folding mechanism is described in “An 8b 150Msample/s Serial ADC” published in 1995 by C. W. Moreland. The initial signal is folded by using a folding amplifier. The result of the fold is then folded a second time by a subsequent folding amplifier and so on until there are n-1 folds in the waveform for an n-bit converter. The number of folding amplifiers, therefore, has decreased from 2
n
to n−1 for an n-bit converter. However, the serial nature of such configurations requires accurate linearity for each folding amplifier. Another technique is to add a post-distorted preamplifier to the folding circuit. However, each of these techniques requires additional power for the circuit.
It would therefore be desirable to provide a linearization technique for a folding amplifier that minimally affects the power associated with such a circuit.
SUMMARY OF THE INVENTION
The present invention provides a folding amplifier architecture with a voltage to current converter linearization technique.
In one aspect of the invention, a linearized folding amplifier circuit includes a comparator that has a first state and a second state, and a switched output circuit that has a pair of outputs. The response of a pair of input transistors is partially linearized by a first resistor connecting the emitters of the two input transistors. The input is further linearized in response to the first and second state-controlling pairs of transistors and a differential error voltage therebetween. The output of the circuit is the combination of the partially linearized portion from the first resistor and the output of a linearized transconductor circuit that has been formed in response to the differential error.
The folding amplifier circuit described above may be included in an analog-to-digital converter.
In a further aspect of the invention, a method of operating a folding amplifier circuit comprises generating output signals from a control circuit in a first state and a second state. In response to the first and second states, a switched output transconductance circuit having a first input transistor pair receiving a first differential input signal is controlled. A first resistor is connected between the emitters of the first input differential pair. A first pair of output transistors having a first transistor and a second transistor and a second pair of output transistors having a third transistor and a fourth transistor are also included in the transconductance circuit. The linear transconductor portion has a third pair of output transistors having a fifth transistor and a sixth transistor and a fourth pair of output transistors having a seventh transistor and an eighth transistor. The third pair is coupled to the first pair and the fourth pair is coupled to the second pair. The linear transconductor portion has a fifth pair of transistors having a ninth transistor and a tenth transistor each having an emitter coupled to a second resistor.
In a first state, a first differential error signal is generated between the first and fourth transistors which corresponds to the error between the transistors of the input differential pair. The first differential error signal is coupled to the linear transconductor portion through the fifth and eighth transistors. The linearized transconductor portion generates a first pair of linearized outputs in response to the first differential error signal and the differential input signal.
A second state is generated by a switching of the control circuit which may be a comparator circuit, such that each of its complementary outputs reverses polarity. In this second state, a second differential error signal is generated between the second and third transistors which corresponds to an error between the transistors of the input differential pair. The second differential error signal is coupled to the linear transconductor portion through the sixth and seventh transistors. The linearized transconductor portion generates a second pair of linearized outputs in response to the second differential error signal and the differential input signal.
One advantage of the invention is that the folding amplifier output exhibits higher linearity than known pre or post-distortion circuits. Further, no extra stage for linearization is included. Although a small number of additional transistors are required, less power is consumed by the circuit than other known techniques. Thus, the performance of an analog-to-digital circuit, in which the linearity of the folding amplifier is directly related to the performance of the converter, is improved.
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patent: 3848195 (1974-11-01), Kiko
patent: 4340866 (1982-07-01), Metz
patent: RE31545 (1984-03-01), Quinn
patent: 4599602 (1986-07-01), Matzuzawa et al.
patent: 4862102 (1989-08-01), LaVoie
patent: 5554943 (1996-09-01), Moreland
patent: 5684419 (1997-11-01), Murden et al.
patent: 6069579 (2000-05-01), Ito et al.
patent: 6163290 (2000-12-01), Moreland et al.
A 3.2-GHz Second-Order Delta-Sigma Modulator Implemented in InP HBT Technology; Jensen, J.F.; Raghavan, G.; Cosand, A.E., Walden, R.H.; IEEE Journal of Solid-State Circuits, vol. 30, No. 10, Oct. 1995.
An 8b 150MSample/s Serial ADC; Moreland, Carl W.; IEEE Internationa Solid-State Circuits Conference, Oct. 1995.
Cosand Albert
Morton Susan
Gudmestad Terje
Nguyen Patricia
The Boeing Company
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