Linearized digital phase-locked loop

Details Linearized digital phase-locked loop Linearized digital phase-locked loop

2006-01-31

2006-01-31

Tse, Young T. (Department: 2637)

Pulse or digital communications

Synchronizers

Self-synchronizing signal

C375S371000, C370S516000

Reexamination Certificate

active

06993105

ABSTRACT:
A method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal and a position of the first edge, (B) determining if the position is within a zone, (C) if the edge is not within the zone, adjusting the clock signal towards the position of the edge, (D) detecting a second edge of the data signal and a position of the second edge, (E) determining a in value indicating a position of the second edge, (F) adding the first value to a second value, wherein the second value indicates a position of a third edge of the data signal and (G) adjusting the clock signal based on the result of step (F).

REFERENCES:
patent: 4151485 (1979-04-01), LaFratta
patent: 4330759 (1982-05-01), Anderson
patent: 4523301 (1985-06-01), Kadota et al.
patent: 4672447 (1987-06-01), Moring et al.
patent: 5059924 (1991-10-01), JenningsCheck
patent: 5343439 (1994-08-01), Hoshino
patent: 5568416 (1996-10-01), Kawana et al.
patent: 5671258 (1997-09-01), Burns et al.
patent: 5757858 (1998-05-01), Black et al.
patent: 5812619 (1998-09-01), Runaldue
patent: 5841823 (1998-11-01), Tuijn
patent: 5889436 (1999-03-01), Yeung et al.
patent: 5901110 (1999-05-01), Jang
patent: 6301188 (2001-10-01), Weber et al.
patent: 6366145 (2002-04-01), Williams et al.
patent: 6380703 (2002-04-01), White
patent: 6385267 (2002-05-01), Bowen et al.
patent: 6417698 (2002-07-01), Williams et al.
patent: 6535023 (2003-03-01), Williams et al.
patent: 6711226 (2004-03-01), Williams et al.
patent: 6760389 (2004-07-01), Mukherjee et al.
Bertrand J. Williams et al., “Linearized Digital Phase-Locked Loop”, U.S. Appl. No. 09/745,660, Filed Dec. 21, 2000.
Bertrand J. Williams et al., “Linearized Digital Phase-Locked Loop Method”, U.S. Appl. No. 09/747,281, Filed Dec. 21, 2000.
Bertrand J. Williams et al., “Linearized Digital Phase-Locked Loop”, U.S. Appl. No. 09/747,262, Filed Dec. 22, 2000.
Timothy J. Jordan et al., “Linearized Digital Phase-Locked Loop Method”, U.S. Appl. No. 09/747,188, Filed Dec. 22, 2000.
Bertrand J. Williams et al., “Linearized Digital Phase-Locked Loop Method”, U.S. Appl. No. 09/746,802, Filed Dec. 22, 2000.

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