Amplifiers – With semiconductor amplifying device – Including differential amplifier
Patent
1990-05-31
1992-01-07
Mullins, James B.
Amplifiers
With semiconductor amplifying device
Including differential amplifier
330261, 330295, H03F 345
Patent
active
050795155
ABSTRACT:
Disclosed is a linearized differential amplifier, comprising connecting input terminals and output terminals of the differential pairs respectively in parallel; arranging N sets of differential pairs (where N is an integer of at least 3); an offset voltage generating circuit for supplying different and equivalent offset voltages to the respective differential pairs; a circuit for weighting these output currents; and a circuit for adding the output currents. Particularly, the offset voltage generating circuit and the weighting circuit carry out equivalent weighting of the offset voltages and the output currents so that the change of the differential output current corresponding to the change of the differential input voltage shows an equal ripple characteristic. Moreover, to give equivalent offset voltages to the respective differential pairs, a linearized differential amplifier where emitter areas in respective differential pairs are different is disclosed. In this case, the ratio of emitter areas is 1:7.872983 and 1:1 when N is 3, and 1:13.40261 and 1:2.030215 when N is 4.
REFERENCES:
patent: 4516081 (1985-05-01), Katakura
patent: 4723110 (1988-02-01), Voorman
patent: 4794348 (1988-12-01), McGinn
James C. Schmoock, "An Input Stage Transconductance Reduction Technique for High-Slew Rate Operational Amplifiers", IEEE Journal of Solid-State Circuits, vol. SC-10, No. 6, Dec. 1975, pp. 407-411.
Kabushiki Kaisha Toshiba
Mullins James B.
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