Linearization technique for phase locked loops employing...

Details Linearization technique for phase locked loops employing... Linearization technique for phase locked loops employing...

2005-09-06

2005-09-06

Vo, Nguyen T. (Department: 2685)

Telecommunications

Transmitter and receiver at same station

With frequency stabilization

C455S118000, C455S260000, C375S374000, C327S157000

Reexamination Certificate

active

06941116

ABSTRACT:
A differential linear fractional N-synthesizer includes a phase and frequency detection module, a linearized charge pump, a low pass filter, a voltage controlled oscillator, and a fractional N divider feedback. The phase and frequency detection module is operably coupled to produce a differential charge-up signal, a differential charge-down signal, or a differential off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The feedback oscillation is generated by the fractional N divider feedback, which divides an output oscillation by a divider value to produce the feedback oscillation. The linearized charge pump includes a 1stcurrent source, a 2ndcurrent source and a modulation module. In response to the differential off signal, the modulation module produces a modulated differential off signal that causes the 1stand 2ndcurrent sources to produce a zero current signal in an alternating fashion. The low pass filter is operably coupled to attenuate the high frequency signal components produced by the modulation module of the linearized charge pump and to pass the positive, negative or zero current signals to produce a filtered signal. The voltage control oscillator produces the output oscillation based on the filtered signal.

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Orcioni S et al: “An 800 MHz 0.35/spl mu/m CMOS clock tree and PLL based on a new charge-pump circuit” 9THInternational Conference on Electronics, Circuits and Systems, vol. 2, Sep. 15-18, 2002, pp. 571-574, XP010614413; p. 572, paragraph 2—p. 573, paragraph 1; figures 3-6.

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