Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular frequency control means
Reexamination Certificate
1998-04-21
2001-09-04
Grimm, Siegfried H. (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular frequency control means
C331S057000, C331S1170FE
Reexamination Certificate
active
06285263
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an electrical circuit, and more particularly it relates to a technique for linearizing the output response of a voltage controlled oscillator.
BACKGROUND OF THE INVENTION
Voltage controlled oscillators (VCOs) are used within phase-locked loops (PLL) for clock synthesis, bit synchronization, etc. (refer to “Phase-Locked Loops”, by R. Best, for background descriptions of operation and applications of PLLs). Voltage controlled ring oscillators tend to have a nonlinear transfer characteristic. This is due to the inherently nonlinear response of the current controlled oscillator which is a subcircuit of the VCO. Most designs assume linearity, which can be a reasonable approximation for small increments. However, prior techniques for implementing PLLs generally do not exhibit such linearity across a wide frequency range of operation.
A typical phase-locked loop is shown at
50
in FIG.
10
. The input reference phase
52
is compared at
58
to the output
54
of the VCO
62
. The charge pump
59
regulates the amount of charge on the loop filter
60
. The output
61
of the loop filter
60
is a voltage that controls the frequency of the oscillator
62
. A VCO
62
typically consists of two stages: a voltage-to-current (V-I) converter, and a current controlled oscillator (ICO). The VCO output frequency varies proportionally to the input voltage of the V-I converter.
For the design of PLLs, it is desirable to have a linear response across the entire frequency range of operation. This helps maintain stability and tracking in the PLL. U.S. Pat. No. 5,477,198, entitled “Extendible-Range Voltage Controlled Oscillator”, and which is hereby incorporated herein by reference, teaches a technique for extending and linearizing the transfer characteristic of a voltage controlled oscillator. While feasible, this technique requires a booster inverter biasing scheme.
SUMMARY OF THE INVENTION
The present invention is directed to a voltage controlled oscillator (VCO) having a generally linear transfer characteristic across a wide frequency range of operation. The VCO includes of a voltage-to-current converter (V-I) and a current-controlled oscillator (ICO). A linearization of the output response of the VCO is accomplished by proper selection of the output responses of the V-I and ICO circuits, where the V-I portion is designed to have an inverse nonlinearity response as compared to the nonlinear response of the ICO portion of the VCO. The combined effect is a linear response for the VCO. A nonlinear V-I characteristic can be achieved by combining several individual piecewise linear responses together to produce a combined piecewise linear signal having a nonlinear response. Thus, the technique compensates for the inherently nonlinear response of an ICO by implementing a nonlinear V-I which controls the ICO.
It is an object of the present invention to provide an improved phase-locked loop circuit.
It is another object of the present invention to provide an improved voltage controlled oscillator circuit.
It is yet another object of the present invention to provide a voltage controlled oscillator having linear characteristics.
It is still another object of the present invention to provide a voltage controlled oscillator having linear characteristics over a wide frequency range.
It is yet another object of the present invention to provide a signal having non-linear characteristics that are inversely proportional to another non-linear signal.
It is another object of the present invention to approximate a non-linear transfer characteristic with a piecewise linear signal.
Additional benefits and advantages of the present invention will become apparent to those skilled in the art to which this invention relates from the subsequent description of the preferred embodiments and the appended claims, taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 3397367 (1968-08-01), Steel et al.
patent: 3531739 (1970-09-01), Groves
patent: 3546617 (1970-12-01), Westwood
patent: 3569867 (1971-03-01), Ernst
patent: 3886485 (1975-05-01), Takahashi
patent: 3904988 (1975-09-01), Hsiao
patent: 3965418 (1976-06-01), Bauer et al.
patent: 4047126 (1977-09-01), Anderson
patent: 4230953 (1980-10-01), Wilcox
patent: 4254382 (1981-03-01), Keller et al.
patent: 4370629 (1983-01-01), Martin
patent: 4388596 (1983-06-01), Yamashita
patent: 4442412 (1984-04-01), Smith et al.
patent: 4492934 (1985-01-01), Sugimoto
patent: 4568888 (1986-02-01), Kimura et al.
patent: 4700285 (1987-10-01), Szepesi
patent: 4853654 (1989-08-01), Sakurai
patent: 4879530 (1989-11-01), Wilhelm et al.
patent: 4890072 (1989-12-01), Espe et al.
patent: 4918404 (1990-04-01), Vitiello et al.
patent: 4935706 (1990-06-01), Schenberg
patent: 4970472 (1990-11-01), Kennedy et al.
patent: 4975662 (1990-12-01), Takeuchi
patent: 4988955 (1991-01-01), Horie
patent: 5028888 (1991-07-01), Ray
patent: 5041799 (1991-08-01), Pirez
patent: 5070311 (1991-12-01), Nicolai
patent: 5081429 (1992-01-01), Atriss et al.
patent: 5105169 (1992-04-01), Yamazaki et al.
patent: 5121086 (1992-06-01), Srivastava
patent: 5136260 (1992-08-01), Yousefi-Elezei
patent: 5142249 (1992-08-01), Hirotomi
patent: 5198784 (1993-03-01), Fenk
patent: 5208557 (1993-05-01), Kersh, III
patent: 5212459 (1993-05-01), Ueda et al.
patent: 5247265 (1993-09-01), Norimatsu
patent: 5250913 (1993-10-01), Gleichert et al.
patent: 5272453 (1993-12-01), Traynor et al.
patent: 5278522 (1994-01-01), Atriss et al.
patent: 5285114 (1994-02-01), Atriss et al.
patent: 5285173 (1994-02-01), Reynolds
patent: 5300898 (1994-04-01), Chen et al.
patent: 5302920 (1994-04-01), Bitting
patent: 5331295 (1994-07-01), Jelinek et al.
patent: 5379001 (1995-01-01), Neil Hedtke
patent: 5477198 (1995-12-01), Anderson et al.
patent: 5483195 (1996-01-01), Brown
Kurt M. Ware et al.; A 200-Mhz CMOS Phase-Locked Loop with Dual Phase Detectors; Dec., 1989; pp. 1560-1568, IEEE Journal of Solid State Circuits, vol. 24, No. 6.
Deog-Kyoon Jeong et al.; Design of PLL-Based Clock Generation; Apr., 1987; pp. 255-261, IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2.
A Low Jitter 5 Mhz to 180 Mhz Clock Synthesizer for Video Graphics; Reza Shariatdoust et al.; IEEE 1992 Custom Integrated Circuits Conference; Mar. 5, 1992; pp. 24.2.1 -24.2.5.
Grimm Siegfried H.
LSI Logic Corporation
LandOfFree
Linearization method and apparatus for voltage controlled... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Linearization method and apparatus for voltage controlled..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Linearization method and apparatus for voltage controlled... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2476095