Linearity error compensator

Details Linearity error compensator Linearity error compensator

2001-01-18

2002-02-05

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Converter compensation

C341S120000

Reexamination Certificate

active

06344810

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a method and apparatus for linearity error compensation in electronic devices, and more particularly to phase-shift exponential processing methods and apparatus for compensating linearity errors (such as harmonic or intermodulation distortion).
BACKGROUND OF THE INVENTION
Linearity errors, also known as nonlinear distortion, in electronic devices are caused by many different factors, primarily in the analog electronics of a system, such as buffer amplifiers, power amplifiers, sample-and-hold amplifiers, analog-to-digital converters, digital-to-analog converters, or electro-mechanical components such as microphones and loudspeakers. These devices introduce nonlinear effects into the system such as asymmetry in the input/output function, clipping, overloading effects, harmonic distortion, and intermodulation distortion.
For example, although the output y of an ideal amplifier is related to its input x by the linear equation y=gx (where g is the gain of the amplifier), the relationship between the input and output of a real amplifier is characterized by the equation y=a
0
+a
1
x+a
2
x
2
+a
3
x
3
+. . . , where the exponential terms (e.g., a
2
x
2
, a
3
x
3
) represent nonlinear distortion introduced by the real amplifier. Other real signal processing devices introduce similar nonlinear distortion into their output. As a result, the outputs of real signal processing devices differ from the desired, ideal outputs.
Linearity errors in electronics severely limit the performance of systems. Linearity errors typically increase as the speed or bandwidth of the device is increased, which limits the resolution or dynamic range of the device. Designers typically face the challenge of trading off resolution of the device with its speed. Increasing the speed and resolution of electronics can offer numerous advantages, including the following: improved dynamic range which increases call capacity in cellular communications systems; increased modulation density (such as larger Quadrature Amplitude Modulation grid spacing) for wider bandwidth digital communications; wideband analog-to-digital conversion or digital-to-analog conversion for compact, universal software-reconfigurable transceivers; improved accuracy of Radar systems and medical imaging equipment; improved speech recognition by compensating for linearity errors in microphones; and high-performance test equipment such as oscilloscopes, spectrum analyzers, or data acquisition systems.
Many electronic systems such as receivers and test equipment use filtering to compensate for gain and phase errors across frequency. A pseudo-random noise signal is periodically injected into the system and the output is re-calibrated for constant gain and phase performance. Since this prior art technique uses a linear filtering operation, it does not correct nonlinear distortion and therefore does not improve the dynamic range.
A common prior art technique for reducing linearity errors is by adding noise or “dither” to the system to essentially randomize the nonlinear distortion. Statistically, dither signals can cause the nonlinear distortion to be signal independent, uniformly distributed white noise. This technique can offer up to 10 dB reduction in harmonic and intermodulation distortion, but at the expense of increasing the noise in the system, which decreases the signal-to-noise ratio.
Another prior art technique for linearity error compensation is a static look-up table (such as a read-only memory) to correct the digital signal. The static look-up table is a two-column table, where the first column contains amplitudes of all possible output signals output by the signal processing device, and where the second column contains the corresponding desired corrected output signal amplitudes. When the signal processing device produces an output signal, the output signal's amplitude is used as an index into the static compensation table, which outputs the corresponding corrected output value. This technique is effective for errors caused by resistor component variance in the comparator ladder of analog-to-digital converters and can provide up to 10 dB reduction in harmonic distortion. However, most current high-performance converters use laser trimmed resistors, so this type of error is minimal. In addition, researchers have realized that this type of correction improves the dynamic range of the converter only near the calibration frequency. The static compensation table can be as large as the number of digital states (for example, an n-bit analog-to-digital converter has 2
n
digital states) so a 12-bit analog-to-digital converter requires a compensation table of up to 4096 memory bins.
Referring to
FIG. 1
, another prior art technique for linearity error compensation is phase-plane compensation
10
, which is a dynamic approach since it accounts for errors that are a function of both amplitude and frequency. Like static compensation, a look-up table
40
is used to correct the digitized samples
15
, but in this case, the lookup table
40
is indexed by the digital signal
15
and the estimated slope
35
of the signal (to account for frequency), as shown in FIG.
1
. This technique accomplishes all that static compensation does but yields improved performance for its ability to compensate errors that are a function of frequency. This technique typically provides 10-15 dB reduction in harmonic distortion. This technique is more hardware-intensive than static compensation since it needs to estimate the slope of the signal
5
and use the slope to index a larger look-up table
40
. For this technique, there is essentially one static compensation table for each slope. So if there are M slopes, each slope getting its own static table, then the size of the table
40
is M×2
n
.
A typical compensation table for an 8-bit device may occupy 32,768 memory bins (256 amplitudes, 128 slopes). Also, inaccurate slope estimates significantly degrade the performance. In addition, this technique is not suitable for super-Nyquist input frequencies (signals above the Nyquist frequency) due to the ambiguity in the slope. Super-Nyquist compensation is necessary in receiver applications that use intermediate frequency (IF) sampling to alias desired signals down to baseband without the use of mixers (which are typically inaccurate and bulky).
Another prior art technique for linearity error compensation is polynomial compensation, for example, as disclosed in U.S. Pat. No. 5,594,612 to Henrion. This technique uses a polynomial power series to compensate for linearity errors by adjusting the polynomial coefficients to minimize the amplitude of the linearity errors. For example, the output signal, x, of a device is processed with a polynomial power series, y=a
0
+a
1
x+a
2
x
2
+a
3
x
3
+. . . , to output a compensated signal, y; the polynomial coefficients a
0
, a
1
, . . . , are iteratively adjusted and the system output is monitored until the linearity errors are below a certain threshold. However, this technique assumes that the linearity errors generated by the device being compensated are accurately modeled with the polynomial power series. An important parameter missing in this model is the phase-shift of the higher-order linearity error distortion terms (e.g., a
2
x
2
, a
3
x
3
); the level of attenuation of the linearity errors suffers greatly without accounting for phase-shift since this technique assumes that the device generates linearity errors which are either in-phase or out-of-phase with the desired fundamental signal. Many devices generate linearity errors with arbitrary phase-shift, so accurately accounting for the phase-shift of the linearity errors in the device is necessary for accurate compensation. In addition, the polynomial compensation technique does not accurately compensate linearity errors over a wide range of input frequencies, since the polynomial model cannot accurately model linearity errors that change over fre

Affiliated with

Also associated with

Rating

Linearity error compensator does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Linearity error compensator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Linearity error compensator will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2977344