Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2000-05-02
2001-10-09
Wong, Peter S. (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C323S303000, C323S276000, C323S281000
Reexamination Certificate
active
06300749
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to a voltage regulator circuit and, more specifically, to a linear voltage regulator having a low drop out.
BACKGROUND OF THE INVENTION
Voltage regulators having a low drop out (LDO) are used in power management control systems for portable devices such as notebooks, cellular phones and similar devices supplied by a battery.
A good power management control system best utilizes the energy stored in the battery in order to increase the autonomy of the portable device by allowing the use of smaller batteries, thereby reducing the weight and size of the portable devices.
To this aim the voltage regulation at the control system output should have high static and dynamic characteristics and a high current efficiency at any load condition.
The structure of a known LDO linear voltage regulator is disclosed in the book “Analog Devices” in the chapter “Low-Drop_out Regulators” by W. Joung and is shown in FIG.
1
. Such a regulator includes an error amplifier Ae having an output connected to a gate terminal of power PMOS pass transistor.
A reference voltage Vref is supplied to a first input of the error amplifier Ae, while the other input of the same amplifier receives a feedback signal from a voltage divider connected to a conduction terminal of the PMOS transistor.
An input voltage Vin is applied to the other conduction terminal of the PMOS transistor.
A circuit node connecting the PMOS transistor and the voltage divider is the output terminal OUT of the LDO voltage regulator. An output capacitance Co is connected between the output terminal OUT and a ground reference GND. A parasitic resistance ESR is serially connected to this output capacitance.
An optional by-pass capacitance Cb is connected in parallel to the series RC connection including the output capacitance Co and the parasitic resistance ESR.
This circuit structure has an output dominant pole Pout determined by the output capacitance Co according to the following relation:
Pout=1/(2Π*Rout*Co)≅(&lgr;Iload+Ipart)/(2*Co)
Where: &lgr; is the channel length modulation (i.e., the inversion of the Early voltage (the voltage at which saturation lines for different Vgs voltages converge on the Vds axis)), Iload is the load current, and Ipart is the biasing current of the voltage divider.
This pole is movable according to load variations and reaches its maximum value when the regulator supplies the maximum output current.
For instance, the output pole may vary along four decades if the load current passes from 0 to 100 mA when the biasing current Ipart is about 10 &mgr;A.
In general, the dependence from the load current of the output pole renders the compensation of this type of regulator pretty complex; see in this respect the article by C. Simpson: “LDO require proper compensation”; Electronic Design, November 1996.
A second pole Pin of the above disclosed regulator is due to the error amplifier Ae.
Without a proper compensation, the two poles Pout and Pin would render the regulator unstable.
For this reason, a circuit component is always provided to introduce a zero, thereby compensating the effects of the output pole Pout. This circuit component is the parasitic resistance ESR that generates a zero at the following frequency:
Zesr=1/(2Π*ESR*Co)
This compensation is critical because in order to guarantee the regulator stability, the resistance value ESR must be kept within a predetermined range of values.
As a matter of fact, if ESR is reduced, the zero frequency Zesr is increased and is moved toward the right side of the pole-zero diagram thereby reducing the compensation effect on the output pole.
On the contrary, if the ESR value is increased, the zero frequency Zesr is reduced and is moved toward the left side of the pole-zero diagram with the risk of introducing further poles and rendering the system unstable.
Unfortunately, the series resistance ESR is a parasitic component of the output capacitance and its value may not be determined with high precision.
For this reason the known LDO regulators are provided with a diagram reporting the range of those ESR resistance values that guarantee stability for the voltage regulator.
Care must be taken in choosing the output capacitance Co. For instance an Aluminium electrolytic capacitor should not be used since its ESR value varies with temperature. Other kind of capacitors, such as ceramic capacitors or OS-CON capacitors cannot be used because of their low ESR value.
Tantalum capacitors may be suitable since their ESR resistance value is stable with temperature and close to the central value of the stability range.
The presence of the series resistance ESR depresses the loading transient of the voltage regulator. The voltage output drop is directly proportional to the value of the resistance ESR serially connected to the output capacitance Co.
The by-pass capacitance Cb may be added to reduce the effect of the resistance ESR, but such a further capacitance increases the costs and the circuit area and brings also a further pole at a frequency:
Pb≅1/(2Π*ESR*Cb)
There has yet to be produced an LDO linear voltage regulator which overcomes the inherent limitations of output compensation problems.
SUMMARY OF THE INVENTION
Embodiments of the present invention overcome these limitations by improving the response characteristics of an LDO voltage regulator by varying the compensation.
These embodiments perform this variable compensation without using a compensation resistance ESR to stabilize the amplifier loop of the voltage regulator, as in the prior art.
Still further embodiments of this invention provide an LDO voltage regulator including ceramic capacitors that have a smaller size, smaller charge time and a better reliability if compared with Tantalum capacitors used in the known regulators.
These advantages are reached by using an adaptive compensation technique that we will hereinafter call Zero Mobile Compensation (ZMC), since it provides in the circuit response a zero capable of moving according to the load variations.
More specifically the inventive LDO linear voltage regulator includes a zero that is moved toward higher frequencies according to the movements of the output pole Pout.
REFERENCES:
patent: 4908566 (1990-03-01), Tesch
patent: 5105102 (1992-04-01), Shioda
patent: 5631598 (1997-05-01), Miranda et al.
patent: 5686821 (1997-11-01), Brokaw
patent: 5861736 (1999-01-01), Corsi et al.
patent: 5939867 (1999-08-01), Capici et al.
patent: 6040736 (2000-03-01), Milanesi et al.
patent: 0 810 504-A1 (1997-12-01), None
patent: 0 864 956-A2 (1998-09-01), None
Castelli Claudia
Villa Francesco
Galanthay Theodore E.
Iannucci Robert
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Vu Bao Q.
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