Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1997-12-30
2001-12-04
Ngo, Chuong Dinh (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S402000
Reexamination Certificate
active
06327601
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates to digital video image processing and more particularly to a linear transform circuit for decoding video data.
BACKGROUND OF THE INVENTION
Images displayed on a video display may be digitally encoded, transmitted, and decoded. Digital encoding of video images offers many well-known advantages. For example, the effects of electromagnetic interference or noise may be reduced with digital data transmission techniques. In addition, conversion of video images into digital signals allows the video images to be processed with digital signal processing techniques, and also makes the video images compatible with other digital data processing technology.
Nevertheless, conversion of a video image into digital data creates a relatively large amount of digital data. A video image typically comprises a large number of picture elements (pixels). A pixel is the smallest resolvable spatial information element of a video display as seen by the viewer. A common display resolution is VGA which consists of 480 lines of 640 pixels each. Thus, each screen requires 307,200 pixels. In addition, color video images are comprised of three separate color pixel subdivisions at each pixel location, which results in 921,600 color pixel subdivisions for each screen. Full motion video requires the transmission of 30 screen images per second, which could require a total of 27.648 million pixels per second if each pixel is transmitted for each screen image.
Even if each pixel could be represented by a single bit of data, a 27.648 megabit data transmission rate would significantly limit the use of digital video data transmission. In practice, each pixel requires eight bits of data for MPEG compatible video. Therefore, it is necessary to compress the digital data using various techniques. Many image compression techniques have been developed.
One class of image compression techniques involves compression algorithms based on a frequency transform. In this technique, the image is generally divided into blocks of fixed size, such as 8×8 pixels. Each block is then transformed from the spatial domain to a frequency domain using a linear transform. The linear transform most commonly used for this operation is the discrete cosine transform (DCT). The discrete cosine transform has been developed in accordance with the moving pictures experts group (MPEG) algorithms, which are industry-standard algorithms used to coordinate digital signal processing of digitally-encoded video signals.
Known linear transform systems for decoding digitally-encoded video data, may involve a system that includes implementation of a binary algorithm as an electronic circuit, such as the discrete cosine transform and its inverse. Various algorithms and electronic circuits have been proposed for these linear transform systems. Nevertheless, these algorithms and electronic circuits suffer from various drawbacks. One such drawback is that a large number of discrete devices must be used in electronic circuits for such algorithms. Another drawback is that the processing time for systems implementing known algorithms may be excessive as the number of electronic circuit elements decreases. These problems are exacerbated for inverse discrete cosine transform (IDCT) circuits, which are typically used in applications that require circuit sizes to be minimized, such as at a set-up box that would be installed at a user's television set.
SUMMARY OF THE INVENTION
Therefore a need has arisen for a linear transform system for decoding digitally-encoded video data which substantially eliminates or reduces disadvantages and problems associated with previously developed linear transform system for decoding digitally-encoded video data.
In particular, a linear transform system for decoding digitally-encoded video data is required that reduces the number of discrete devices required to implement the circuit, and which reduces the amount of processing time required to process data as compared with other circuits having the same number of electronic components.
In accordance with the present invention, a linear transform system for decoding video data is provided. The system includes inputs connected to a circuit for implementing a decoding algorithm that includes a multiplication circuit stage having a multiple output scaler structure. A bit-serial operator stage is connected in series with the multiplication circuit stage. The bit-serial operator stage is coupled to a plurality of outputs that generate decoded video data.
The present invention provides many important technical advantages. One important technical advantage of the present invention is a linear transform system for decoding video data that minimizes the number of discrete components required to implement the circuit. The linear transform system for decoding video data of the present invention is optimized to decrease the number of discrete components and subsequently decrease the circuit size.
Another important technical advantage of the present invention is a linear transform system for decoding video data with decreased processing time. The linear transform system for decoding video data of the present invention compresses digitally encoded video data in less time than known linear transform systems for decoding video data having the same number of electronic components.
REFERENCES:
patent: 5394349 (1995-02-01), Eddy
patent: 5636152 (1997-06-01), Yang et al.
patent: 5701263 (1997-12-01), Pineda
patent: 5748514 (1998-05-01), Okada et al.
patent: 5781239 (1998-07-01), Mattela et al.
Brady III Wade James
Franz Warren L.
Ngo Chuong Dinh
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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