Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2002-06-07
2003-08-26
Choe, Henry (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S257000
Reexamination Certificate
active
06611171
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a differential amplifier, and more particularly to a linear transconductance amplifier having a linear transconductance formed on a semiconductor integrated circuit.
2. Description of Related Art
Conventionally, this kind of a CMOS linear transconductance amplifier, such as a circuit shown in
FIG. 7
of the publication; IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL-CAS32, NO.11, NOVEMBER 1985, PP. 1097-1103, “CMOS Voltage to Current Transducers”, realizes a linear operation by executing a subtraction of the drain currents of the two MOS transistors M
1
and M
2
having the square-law characteristic with respect to the input voltage. This scheme is well known, and an operation of the circuit having such an output circuit arrangement is referred to as a class AB operation.
Neglecting an effect depending of a substrate and an influence of channel length modulation, and assuming that the relation between the drain current and the gate-source voltage of a MOS transistor operating in a saturation region obeys the square-law, the drain current of the MOS transistor is expressed as follows:
I
D
=&bgr;(
V
GS
−V
TH
)
2
(
V
GS
≧V
TH
) (1a)
I
D
=0(
V
GS
≦V
TH
) (1b)
where &bgr;=&mgr; (C
ox
/2) (W/L) is a transconductance parameter, &mgr; is an effective mobility of carrier, C
ox
is a gate oxide film capacity per unit area, W and L are a gate width and a gate length, respectively, and V
TH
is a threshold voltage.
Referring to the left of
FIG. 7
, there is a relationship as follows:
V
in
=V
GS1
+V
GS2
−[V
GS3
+V
GS4
] (2)′
Equation (2)′ can be reduced to the following equation (2).
V
in
=V
GSeq
−(
V
b
+V
THeq
) (2)
Here, if a CMOS-pair consisting of an N-channel MOS transistor and a P-channel MOS transistor is regarded as one complex transistor, V
GSeq
, &bgr;
eq
, and V
THeq
are expressed as follows:
V
GSeq
=
V
THeq
+
1
β
eq
2
I
(
3
)
β
eq
=
β
N
β
P
(
β
N
+
β
P
)
2
(
4
)
V
THeq
=
V
THN
+
V
THP
(
5
)
In addition, V
b
is expressed as follows:
V
b
={square root over (2
I/&bgr;
eq
)} (6)
From Equation (3), the following equation (7) is obtained:
V
in
=
2
I
1
β
eq
-
V
b
(
7
)
Referring to the left of
FIG. 7
, the current I
1
is expressed as follows:
I
1
=&bgr;
eq
/2(
V
b
+V
in
)
2
(8)
Similarly, referring to the right of
FIG. 7
, the current I
2
is expressed as follows:
I
2
=&bgr;
eq
/2(
V
b
−V
in
)
2
(9)
Consequently, the output current is expressed as follows:
V
out
=I
1
−I
2
=2&bgr;
eq
V
b
V
in
=2{square root over (2&bgr;
eq
I
b
)}V
in
(10)
FIG. 8
is a graph for explaining a linear operation. The input voltage has a linear region as follows:
−{square root over (2
I
b
/&bgr;
eq
)}<V
in
<{square root over (2
I
b
/&bgr;
eq
)} (11)
The output current has a linear region as follows:
−4
I
b
<I
out
<4
I
b
(12)
Essentially, the circuit shown in
FIG. 7
is a multiplier core circuit capable of implementing a multiplier circuit in itself, which is based on the following identity (
13
) providing a multiplying function.
¼{(
x+y
)
2
−(
x+y
)
2
}=xy
(13)
This technique including the value of the coefficient is referred to as “The quarter-square technique” and widely known. Accordingly, the scheme involving the subtraction of the outputs of the square-circuit is regarded as the only linearization scheme. Furthermore, the inventor considers that the scheme in which a two-quadrant multiplier is used as a linear transconductance amplifier is not sophisticated in terms of circuit arrangement, the two-quadrant multiplier being configured by fixing one input side of the multiplier core circuit with a linear transconductance capable of implementing a four-quadrant operation to restrict the same to a two-quadrant operation.
However, since the conventional CMOS linear transconductance amplifier has the P-channel MOS transistor in the signal line for subtraction of the output currents, it is difficult to improve a frequency characteristic thereof.
SUMMARY OF THE INVENTION
In analog signal processings, a differential amplifier is an essential function block. Particularly, a requirement of a MOS differential amplifier with a linear characteristic has been grown. Thus, an object of the present invention is to provide a linear transconductance amplifier which is easily implemented with LSI and superior in a frequency characteristic.
According to a first aspect of the present invention, there is provided a linear transconductance amplifier in which gates of a first and second transistors having their sources grounded are connected to each other to constitute an input terminal pair. The linear transconductance amplifier comprises means for forming an added current by adding two currents substantially equal to the drain currents of the first and second transistors, respectively, a constant current source for outputting a constant current, and means for forming a subtracted current by subtracting the addition current from the constant current. In the linear transconductance amplifier, one differential output current is formed by adding the drain current of the first transistor and a current almost a half of the subtraction current, and the other differential output current is formed by adding the drain current of the second transistor and a current almost a half of the subtraction current. Further, an input voltage applied to the input terminal pair is a differential voltage superimposed on a constant DC voltage. Transistor described here includes a MOS (metal-oxide semiconductor) transistor, a MIS (metal insulator semiconductor) transistor, and the like.
More particularly, the first linear transconductance amplifier according to the present invention has the following configuration. There is provided a linear transconductance amplifier comprising a first, second, third and fourth N-channel MOS transistors having their sources grounded, a constant current source for outputting a constant current, and a current mirror circuit in which a ratio between an input current and an output current is constant. In the linear transconductance amplifier, gates of the first and third MOS transistors are connected to each other to constitute one terminal of an input terminal pair, and gates of the second and fourth MOS transistors are connected to each other to constitute the other terminal of the input terminal pair. The constant current is separated into two currents, one of which is the sum of drain currents of the third and fourth MOS transistors and the other of which is an input current of the current mirror circuit. Furthermore, the sum of a drain current of the first MOS transistor and an output current of the current mirror circuit constitutes one differential output current, and the sum of a drain current of the second MOS transistor and an output current of the current mirror circuit constitutes the other differential output current.
In the second liner transconductance amplifier according to the present invention, gates of a first and second transistors having their sources grounded are connected to each other, and further connected to the drains of the first and second transistors through resistors, respectively, and gates of a third and fourth transistors having their sources grounded are connected to the drains of the first and second transistors, thereby constituting an input terminal pair. The linear transconductance amplifier comprises means for forming an added current by adding two currents substantially equal to drain currents of the third and fourth transistors, respectively, a constant current source for outputting a constant current, and means for forming a subtracted current by subtracting the addition curre
Choe Henry
NEC Electronics Corporation
Scully Scott Murphy & Presser
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