Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1999-01-12
2001-04-10
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
Reexamination Certificate
active
06215337
ABSTRACT:
BACKGROUND OF THE INVENTION
I. Field of the Invention
The invention relates to analog/radio frequency circuit design. More particularly, the invention relates to an analog/RF switch.
II. Description of the Related Art
A simple switched capacitor sample and hold circuit can be used to convert between an analog continuous time domain and a sampled data domain.
FIG. 1
is a conceptual schematic diagram showing a simple switched capacitor sample and hold circuit. Typically the input signal (&ngr;
in
) is a radio frequency (RF) or intermediate frequency (IF) signal which carries a band-limited, modulated signal. The input signal is applied to a switch
20
which opens and closes at a periodic clock frequency. A capacitor
22
is connected between the output of switch
20
and a common ground. The output voltage is generated across the capacitor
22
. The capacitor
22
is typically a linear poly-poly or metal-metal capacitor. The output signal (&ngr;
o
) is a sampled data signal. The sampling frequency at which the switch
20
is opened and closed must be higher than twice the modulated bandwidth of the input signal in order to satisfy the Nyquist Theorem. Thus, for a narrow-band signal, the sampling rate can be lower than the carrier frequency as long as it is twice the modulated bandwidth. Using a sampling frequency lower than the carrier frequency of the input signal is referred to as subsampling and is used to downconvert the input signal to a lower frequency.
The spectrum of the output signal contains copies of the input signal centered around multiples of the sampling frequency. For example, the spectral content of the output signal (ƒ
out
) can be expressed as shown in Equation 1.
ƒ
out
=nƒ
clk
±ƒ
in
(1)
where:
ƒ
clk
is equal to the sampling frequency;
ƒ
in
is equal to the frequency of the input signal; and
n is equal to 0, 1, 2, 3 . . . .
The output signal can be filtered to reduce the power level at the undesired frequencies. For instance, if the input signal is centered on a carrier at 240 megahertz (MHz) and the sampling circuit is clocked at 60 MHz, a replica of the modulated input signal appears at baseband, 60 MHz, 120 MHz, 180 MHz, as well as at several higher frequencies. The replicas above the baseband frequency can be filtered such that only the baseband replica is preserved.
The on resistance of the switch
20
is not ideal and, therefore, the switch
24
exhibits ohmic resistance even when the switch
20
is closed.
FIG. 2
is a schematic diagram showing an equivalent circuit when the switch
20
is closed. A resistor
26
represents the on resistance of the switch
20
. Due to the resistive nature of the closed switch, the output signal is related to the input signal in accordance with Equation 2, below.
v
o
=
v
in
1
+
sRC
(
2
)
where:
&ngr;
in
is the voltage level of the input signal;
&ngr;
out
is the voltage level of the output signal;
C is the capacitance value of capacitor; and
R is the on-resistance of the closed switch.
It is evident from examining Equation 2 that the switched capacitor sampling circuit acts as a low pass filter.
In reality, the resistive value of the switch
20
is not constant and instead is a function of the voltage level of the input signal.
FIG. 3
is an x/y graph showing the resistive value of an exemplary single nMOSFET switch as a function of the voltage level of the input signal. In
FIG. 3
, the horizontal axis represents the input signal voltage level in volts. The vertical axis represents the ohmic resistance of the switch on a logarithmic scale in Ohms (&Sgr;). As shown in
FIG. 3
, the on resistance of a FET is a strong function of the voltage level of the input signal which is applied to it.
Taking into consideration the curve shown in
FIG. 3
, Equation 3 more accurately reflects the effect of the on resistance of the switch
20
.
v
o
=
v
in
1
+
sR
(
vin
)
C
(
3
)
where:
R(&ngr;
in
) is equal to the voltage level dependent on resistance of the closed switch.
By examining Equation 3, one can see that not only does the switch act as a low pass filter but, in addition, the response of the low pass filter is a function of the voltage level of the input signal. For this reason, the switch is nonlinear and tends to create extremely high levels of distortion to the output signal.
FIG. 4
is a schematic diagram showing a parallel nMOSFET and pMOSFET (metal oxide semi-conductor field effect transistor) switch
24
. The parallel switch
24
conducts signals so long as the voltage range of the input signal remains within the power supply voltages used to bias it. The parallel switch
24
exhibits substantially less variance in on resistance as a function of input signal level and, therefore, provides a more linear response.
FIG. 5
is an x/y graph showing the resistive value of a prior art parallel switch as a function of the voltage level of the input signal. In
FIG. 5
, the horizontal axis represents the input signal voltage level in volts. The vertical axis represents the ohmic resistance of the parallel switch in Ohms (&Sgr;). Notice that between 1.0 to 1.4 Volts (V) the resistance of the switch varies by about 2.5 (i.e. R(&ngr;
in
=1)*2.5=R(&ngr;
in
=1.4). Such high levels of variance of on resistance as a function input voltage can cause significant distortion in the sampling process.
The frequency response of the on-resistance of prior art parallel switches is also dependent on the input voltage level.
FIG. 6
is an x/y graph showing the frequency response of a prior art parallel switch. The solid curve
28
represents the frequency response of the parallel switch at an input voltage level of 1.4V. The dotted curve
30
represents the frequency response of the parallel switch at an input voltage level of 1.0V.
FIG. 7
is an x/y graph showing the phase response of a prior art parallel switch. The solid curve
32
represents the phase response of the parallel switch at an input voltage level of 1.4V. The dotted curve
34
represents the phase response of the parallel switch at an input voltage level of 1.0V. The divergence of the high frequency characteristics as a function of the input signal contributes additional nonlinearities to the performance of the switch and tends to more greatly distort the output signal.
When a switch with such non-linear properties is used to subsample a high frequency RF signal, the resultant samples are distorted. Therefore, the resultant samples do not accurately reflect the actual characteristics of the RF signal. As the distorted samples are subject to further processing within the receiver, the distortion produces errors. The errors can be so significant that using the switches at high frequencies is not practical and more expensive, larger and power-hungry down-conversion methods must be employed.
For these reasons, there is a need in the industry to develop a switch which exhibits a more linear response.
SUMMARY OF THE INVENTION
A linear switch is constructed with a p-channel and an n-channel field effect transistor (FET). A source node of the p-channel FET is coupled to a drain node of the n-channel FET to form a terminal of the switch. A drain node of the p-channel FET is coupled to a source node of the n-channel FET to form another terminal of the switch. The n-channel FET has a n-channel width. The p-channel FET has a p-channel width. The p-channel width is larger than the n-channel width in order to increase the linearity of the on-resistance of the resulting switch as a function of input voltage applied to one terminal and output voltage produced at the other terminal.
In one embodiment, a sampling capacitor is coupled to an output terminal of the switch. An input terminal of the switch is connected to a band-limited, modulated signal. Complementary clock signals are coupled to the gate node of the p-channel FET and the gate node of the n-channel FET. The complementary clock signals operate at a lower frequency than a center frequency of the band-limited, modulated signal. The output ter
Brown Charles D.
Hom Raymond
Nu Ton My-Trang
Qualcomm Incorporated
Wadsworth Philip
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