Linear regulator enhancement technique

Details Linear regulator enhancement technique Linear regulator enhancement technique

2001-09-19

2003-01-21

Riley, Shawn (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C327S541000, C327S542000

Reexamination Certificate

active

06509727

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a voltage regulator such as a linear voltage regulator and the associated circuitry.
BACKGROUND OF THE INVENTION
A DC-to-DC voltage regulators typically are used to convert a DC input voltage to either a high or a low DC output voltage. One type of voltage regulator, called a linear regulator, is often chosen due to its simple design.
Referring to
FIG. 1
, a linear regulator may use a transistor
106
to conduct current from an input voltage source
116
(providing a voltage called unfiltered supply voltage) to a load
102
that is coupled to an output terminal
120
of the regulator
100
. To regulate an output voltage (called V
OUT
), the regulator
100
may include an error amplifier
114
that amplifies the difference between a reference voltage obtained from reference voltage source
116
and a signal (called V
F
) that is proportional to the output voltage. Due to negative feedback, an error voltage that is formed by the amplifier
114
functions to control the transistor
106
in such a manner as to keep the V
OUT
voltage within prescribed limits. The reference voltage V
REF
may be provided by, for example, a low power voltage reference circuit
116
. Other features of regulator
100
may include an RC filter formed by resistor
110
and capacitor
112
. This low-pass filter filters high-frequency noise through capacitor
112
.
When the regulator
100
powers up, the voltages and currents of regulator
100
fluctuate until the voltages and currents reach steady state, or quiescent, bias levels. Unfortunately, these fluctuations may produce power surges that cause the V
IN
and V
OUT
voltages to vary outside of specified tolerances. For example, the V
IN
and V
OUT
voltages may be supplied by voltage rails of a computer system power supply and may not be able to vary beyond a predetermined percentage (for example, five percent) of the predetermined voltage level, which may be five volts.
To minimize the effects that regulator
100
imposes on the input voltage source during power-up, a limitation may be placed on the slew rate of the regulator
100
. In particular, the slew rate is the maximum rate at which the regulator
100
can change the V
OUT
voltage. By limiting the slew rate, voltage and current fluctuations in the V
OUT
voltage are dampened when the regulator
100
powers up. Unfortunately, designs that limit the slew rate for purposes of regulating the power-up state of the regulator
100
may cause the regulator
100
to respond poorly to transient load conditions during normal operation of the regulator
100
. Thus, there is a continuing need for a regulator having a sufficient slew rate to accommodate the state of the regulator. Additionally, it is necessary to improve the existing power supply rejection ratio (PSRR) without adding undue complexity to the design of the linear regulator.
As illustrated in
FIG. 1
, the unfiltered supply voltage is typically at 3.3 volts, and the load circuit
102
requires voltages ranging from 1.1 volts to 1.8 volts. There are many topologies for linear regulators. In
FIG. 1
, the buffer feedback circuit comes directly from the operational amplifier. Feedback might be taken from the source or emitter of a MOS transistor or a bipolar junction transistor (BJT), as the case may be. The reference circuit
116
could employ an auto-calibration loop; however, the reference voltage might be supplied from a band gap voltage reference circuit. There are many mechanisms that can cause degradation in the PSRR. One of these is the output impedance of transistor
106
. As the unfiltered supply voltage modulates, part of that modulation will transfer from the drain of transistor
106
to the source of the transistor
106
. Additionally, higher frequencies result in increased PSRR. This results from the capacitive parasitic paths found in transistor
106
. Thus, with high-frequency modulation from the unfiltered supply voltage, capacitive coupling can occur from the drain-gate capacitance of transistor
106
, and this high-frequency modulation can be coupled to the load through the gate-source capacitance of transistor
106
.
SUMMARY OF THE INVENTION
The present invention significantly improves the PSRR. More particularly, the present invention improves the PSRR due to voltage modulation that is transferred from the drain of a transistor to the source of the transistor where that transistor is used to connect the voltage supply to the load. Additionally, the present invention improves PSRR due to high-frequency modulation of the unfiltered supply voltage that is coupled through the drain-to-gate capacitance of the transistor used to couple the voltage to the load. This high-frequency modulation is then coupled to the load.


REFERENCES:
patent: 5315231 (1994-05-01), Linder et al.
patent: 5867015 (1999-02-01), Corsi et al.
patent: 5929696 (1999-07-01), Lim et al.
patent: 5939870 (1999-08-01), Nguyen et al.

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