Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2001-11-08
2003-02-18
Sterrett, Jeffrey (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
Reexamination Certificate
active
06522112
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to low-dropout regulators. In particular, the present invention relates to a method and apparatus that provides for compensation in a low-dropout regulator.
BACKGROUND OF THE INVENTION
Voltage regulators provide a relatively constant voltage source to other electronic circuits. Some regulators are limited in their effectiveness in a particular application. For example, some regulators have a high “drop-out” voltage. A “drop-out” voltage is the minimum voltage difference between the input voltage and the output voltage that is necessary to maintain proper regulation. Large drop-out voltages result in wasted power, and raise the minimum power supply requirements for maintaining regulation.
A low-dropout regulator (hereinafter an “LDO regulator”) is useful in applications where it is desired to maintain a regulated voltage that is sufficiently close to the input voltage. For example, LDO regulators are useful in battery-powered applications where the power supply operates at a low voltage. Frequently, an LDO implementation will employ a compensation network on the output stage to improve stability over the operating margins.
Compensation schemes available to a designer include the addition of a so-called “feed-forward” zero within a feed back loop.
FIG. 1
illustrates an LDO regulator (
100
) that includes compensation using a feed-forward zero. The LDO regulator includes an operational amplifier (op-amp,
101
), a PNP transistor (
104
), a first resistor (
103
a
), a second resistor (
103
b
), and a capacitor (
102
). A reference, or band-gap, voltage (V
bg
) is provided to the inverting input of the op-amp (
101
). An output of the op-amp (
101
) is connected to the base of the PNP transistor (
104
). A supply voltage (V
in
) is provided to the emitter of the PNP transistor (
104
). The collector of the PNP transistor (
104
) is connected to an output node. The capacitor (
102
) is series connected from the output node to the non-inverting input of the op-amp(
101
). The first resistor (
103
a
) is series connected from the output node to the non-inverting input of the op-amp (
101
). The second resistor (
103
b
) is connected from the non-inverting input of the amplifier to ground.
The first and second resistors form a voltage divider that provides a negative feedback signal (F
b
) to the non-inverting input of the op-amp (
101
). The band-gap voltage (V
bg
) is typically an internally generated regulated voltage around 1.25 volts, and provided from a high-impedance, low-power voltage source. The supply voltage (V
in
) is generally an unregulated raw supply voltage. The amplifier compares the feedback signal (F
b
) to the band-gap voltage (V
bg
) such that an output voltage (V
out
) is provided at the output node.
The stability of the LDO regulator (
100
) is analyzed for stability by computing a transfer function. The transfer function for LDO regulator (
100
) is:
F
b
(
s
)
V
out
(
s
)
=
R
2
R
2
+
R
1
·
R
1
Cs
+
1
(
R
1
&LeftBracketingBar;
&RightBracketingBar;
R
2
)
Cs
+
1
.
The above transfer function includes a zero (R
1
Cs+1) and a pole ((R
1
∥R
2
)Cs+1). When the zero and the pole are not significantly separated the additional phase margin afforded by the zero is diminished. For example, when R
1
<<R
2
, (R
1
∥R
2
)≅R
1
, and the pole and zero cancel one another. When the output voltage (V
out
) is designed to be close to the reference voltage (V
bg
), R
2
must be much larger than R
1
, and the parallel combination of R
1
and R
2
is approximately equal to R
1
. Therefore the pole is located very close to the zero and the stability margin is not functionally improved. Additionally, most LDO regulator configurations that utilize a feed-forward zero compensation scheme depend upon the ESR of a load capacitor to introduce an additional zero into the feedback loop. Therefore, lower cost capacitors that are low-ESR cannot be used in such designs.
SUMMARY OF THE INVENTION
The present invention is directed to an apparatus and method for an improved LDO regulator. The LDO regulator has improved compensation allowing the regulator to operate with increased stability.
Briefly stated, a method and apparatus is directed to stable compensation of a linear regulator. The linear regulator includes an amplifier that is configured to provide a control signal in response to a comparison between a feedback signal and an output signal. A pass element in the regulator selectively couples power from an unregulated power signal to an output node in response to the control signal. A compensation circuit that includes negative gain is arranged to provide the feedback signal in response to an output signal at the output node. In one example, the compensation circuit includes an inverting amplifier that provides an intermediary signal in response to the output signal, and the intermediary signal is coupled to a feedback network that provides the feedback signal. In another example, the compensation circuit includes an inverting amplifier that cooperates with a feedback network to provide the feedback signal. The closed-loop transfer functions of the compensation circuits provide a feed-forward zero that enables stable operation of the LDO regulator.
A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detail description of presently preferred embodiments of the invention, and to the appended claims.
REFERENCES:
patent: 4908566 (1990-03-01), Tesch
patent: 5850139 (1998-12-01), Edwards
patent: 5889393 (1999-03-01), Wrathall
patent: 5945818 (1999-08-01), Edwards
patent: 5982226 (1999-11-01), Rincon-Mora
patent: 6130527 (2000-10-01), Bontempo et al.
patent: 6259238 (2001-07-01), Hasting
Kotowski Jeffrey P.
Schmoock James Charles
Hertzberg Brett A.
Merchant & Gould
National Semiconductor Corporation
Sterrett Jeffrey
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