Linear regulator capable of sinking current

Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...

Reexamination Certificate

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C323S276000, C323S280000

Reexamination Certificate

active

06377033

ABSTRACT:

This application incorporates by reference Taiwanese application Ser. No. 89115893, filed on Aug. 7
th
, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a linear regulator, and more particularly to a linear regulator which is capable of sinking current and suitable to be employed as the previous stage of a circuitry that may feed the previous stage with current.
2. Description of the Related Art
Referring to
FIG. 1A
, it illustrates a conventional linear regulator for outputting a fixed and stable output voltage Vout. An amplifier
102
receives a reference voltage Vref of positive value at the amplifier's non-inverting input terminal, and the inverting input terminal of the amplifier
102
is connected to node N
1
. Node N
1
is also the common terminal of the resistors R
1
and R
2
in series, and the resistor R
2
is further connected to the ground GND. Finally, the output terminal of the amplifier
102
is connected to the base B
1
of transistor Q
1
. The collector C of the transistor Q
1
is used to receive an input voltage Vin while the emitter E
1
of the transistor Q
1
is connected to the resistor R
1
and capacitor C. In addition, the emitter E
1
is used to output an output voltage Vout.
Referring to
FIG. 1B
, it illustrates the linear regulator in
FIG.1
terminated with a circuitry
104
, the next stage of the linear regulator. An example of circuitry
104
is the input stage of a double data rate random access memory (DDR RAM). The circuitry
104
has two switching operating modes. Specifically, the circuitry
104
can be regard as an equivalent input resistor Rin connecting to the ground or a fixed voltage V
1
through an equivalent switch
106
. The fixed voltage V
1
may be from the data bus of the DDR RAM. When the input resistor Rin is connected to the ground, the operations of the linear regulator in
FIG.1
is as follows. Firstly, when the linear regulator is initialized, the output voltage Vout from the output terminal
100
is zero. Thus, the output of the amplifier
102
is a positive voltage so the transistor Q
1
conducts and the capacitor C is charged. In addition, the current flows through the resistor Rin.
Besides, when the Rin is connected to the fixed voltage V
1
by the switch
106
, there exists a current flowing through the Rin and back to the output terminal
100
, leading to the capacitor C to be charged. The voltage of capacitor C then continues to increase, finally exceeding the limitation of the system. Since the conventional linear regulator only outputs current to the next stage, or the circuitry
104
, but cannot sink the feeding current from the next stage, if the circuitry
104
feeds the previous stage with the current, it may cause the conventional linear regulator not to be able to operate in the operation modes as usual.
The conventional approach to the problem of feeding current from the next stage is using a circuitry as shown in FIG.
2
. In
FIG. 2
, a controller
202
is used to detect the voltage of a node N
2
and turns on or off the transistor Qa and Qb in responsive to the voltage of the node N
2
, where the voltage of the node N
2
corresponds to the output voltage Vout at the output terminal
204
. Like the example in
FIG. 1
, the output terminal
204
is connected to the next stage, circuitry
206
. When the circuitry
206
feeds the linear regulator with current so that the output voltage Vout increases, the controller
202
turns on the transistor Qb, lowering the output voltage Vout.
However, the speed of switching on the transistor Qb controlled by the controller
202
is restricted since the inductance L in
FIG. 2
limits the feeding current from the next stage. Therefore, during the output voltage Vout increasing but the transistor Qb not conducting, in order to prevent the output voltage Vout from exceeding, a capacitor Ca of high capacitance is used to absorb the unnecessary energy from the next stage. In this case, the energy stored in the inductance L is then transferred to the capacitor Ca, affecting the output voltage Vout. Consequently, for lowering the effect of the inductance L on the capacitor Ca, the capacitance of Ca has to be higher. Besides, since large changes in current per unit time occur in the capacitor Ca, a capacitor of high quality and high expense has to be employed as the capacitor Ca. This is because that a high quality capacitor Ca has its equivalent serial inductance and resistor in small values so that the output voltage Vout is prevented from increasing as the current flows through the capacitor Ca.
Thus, the capacitor of high quality and large capacitance has to be used in the conventional linear regulator in
FIG. 2
, leading to the increase in the production cost. Besides, in order to provide good performance, the controller
202
employed in the circuitry of
FIG. 2
has to be accurate in controlling capability. Therefore, it further greatly increases the cost of implementation of the circuitry and hence limits the circuitry's usage.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a linear regulator capable of sinking current. When the output of the next stage of the linear regulator according to the invention changes to a fixed voltage, the linear regulator handles the feeding current from the next stage, resulting in an output voltage restricted within a range under the system limitations. According to the invention, a simple structure of circuitry with only a small number of components is necessary to achieve the identical purpose of the conventional linear regulator for resolving the feeding current from the next stage. Besides, no inductance is employed in the circuitry so that the switching speed, in responsive to the feeding current from the next stage, for handling the problem is rapid. In this way, the linear regulator according to the invention provides a better performance and requires a less production cost, having the advantages over other products.
In accordance with the object of the invention, it provides a linear regulator capable of sinking current, outputting an output voltage at an output terminal of the linear regulator. The output terminal provides a next stage with the output voltage while the next stage feeds the linear regulator with current. The linear regulator includes a first transistor, a second transistor, a first amplifier, and a second amplifier. The first transistor, which is connected to the output terminal of the linear regulator, is used for receiving an input voltage. The first amplifier has a first non-inverting input terminal, a first inverting input terminal, and a first output terminal. The first non-inverting input terminal is used for receiving a first reference voltage. The first output terminal, which is connected to the first transistor, is used for controlling the first transistor. The first inverting input terminal is used for receiving a first voltage that corresponds to the output voltage. The second transistor is connected to the output terminal of the linear regulator. The second amplifier has a second non-inverting input terminal, a second inverting input terminal, and a second output terminal. The second non-inverting input terminal is used for receiving a second voltage that corresponds to the output voltage. The second inverting input terminal is used for receiving a second reference voltage, where the second reference voltage is greater than the first reference voltage. The second output terminal, which is connected to the second transistor, is used for controlling the second transistor. When the second voltage is greater than the second reference voltage, the second transistor conducts and sinks the current from the next stage.
In addition, the next stage can be the input stage of a double data rate random access memory (DDR RAM).


REFERENCES:
patent: 5864227 (1999-01-01), Borden et al.
patent: 5982226 (1999-11-01), Rincon-Mora
patent: 6201375 (2001-03-01), Larson et al.

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