Linear load MOS transistor circuit

Details Linear load MOS transistor circuit Linear load MOS transistor circuit

1978-12-18

1980-04-08

Mullins, James B.

Amplifiers

With semiconductor amplifying device

Including signal feedback means

330277, H03F 316, H03F 134

Patent

active

041975111

ABSTRACT:
The source-drain resistance of an MOS load transistor (M.sub.2) is linearized by means of a pair of properly designed auxiliary MOS transistors (M.sub.3 and M.sub.4) whose source-drain paths are electrically coupled (conductively or through an amplifier) with the load transistor (M.sub.2). The gate electrode of the load transistor (M.sub.2) is connected to the common node point (N.sub.34) between the auxiliary transistors (M.sub.3 and M.sub.4); whereas the transconductances (.beta..sub.3 and .beta..sub.4) of the auxiliary transistors (M.sub.3 and M.sub.4) are designed such that during operation the resulting feedback signal from the common node point (N.sub.34) to the gate electrode of the load transistor (M.sub.2) reduces its nonlinearity.

REFERENCES:
patent: 3806742 (1974-04-01), Powell

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