Pulse or digital communications – Synchronizers
Reexamination Certificate
2007-06-26
2007-06-26
Ghayour, Mohammed (Department: 2611)
Pulse or digital communications
Synchronizers
C375S327000, C375S376000, C327S165000, C327S141000, C327S147000, C327S153000
Reexamination Certificate
active
10259537
ABSTRACT:
There is a clock recovery circuit to correct the timing relationship between a data signal and clock signal. The clock recovery circuit comprises a phase detector having an input for receiving a clock signal having a period, an input for receiving a data signal, and an input for receiving a window signal. The window signal has a period equal to the period of the clock signal and phase difference of −90° with respect to the clock signal. The phase detector generates an up output and a down output while maintaining a phase relationship of the up output and the down output in response to the phase relationship between the clock signal and the data signal.
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den Besten Gerrit
Joordens Geertjan
Ghayour Mohammed
Malek Leila
NXP B.V.
Zawilski Peter
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