Linear half-rate phase detector and clock and data recovery...

Details Linear half-rate phase detector and clock and data recovery... Linear half-rate phase detector and clock and data recovery...

2006-03-21

2006-03-21

Sedighian, M. R. (Department: 2633)

Optical communications

Transmitter and receiver system

Including synchronization

C375S374000, C375S375000, C327S157000, C327S159000

Reexamination Certificate

active

07016613

ABSTRACT:
Method and apparatus for recovering a clock and data from a data signal. One method of the invention includes receiving the data signal having a first data rate, receiving the clock signal having a first clock frequency, alternating between a first level and a second level, wherein the first data rate is twice the first clock frequency. A first signal is generated by passing the data signal when the clock signal is at the first level, and storing the data signal when the clock signal is at the second level. A second signal is generated by passing the data signal when the clock signal is at the second level, and storing the data signal when the clock signal is at the first level. A third signal is generated by passing the first signal when the clock signal is at the second level, and storing the first signal when the clock signal is at the first level. A fourth signal is generated by passing the second signal when the clock signal is at the first level, and storing the second signal when the clock signal is at the second level. An error signal is generated by taking the exclusive-OR of the first signal and the second signal, and a reference signal is generated by taking the exclusive-OR of the third signal and the fourth signal.

REFERENCES:
patent: 4071905 (1978-01-01), Oguchi et al.
patent: 4535459 (1985-08-01), Hogge, Jr.
patent: 5301196 (1994-04-01), Ewen et al.
patent: 5799048 (1998-08-01), Farjad-Rad et al.
patent: 6072337 (2000-06-01), Dalmia et al.
patent: 6121804 (2000-09-01), Bryan et al.
patent: 6181756 (2001-01-01), Moloudi
patent: 6211741 (2001-04-01), Dalmia
patent: 6424194 (2002-07-01), Hairapetian
patent: 6559715 (2003-05-01), Frake et al.
patent: 07099515 (1995-04-01), None
patent: WO 01/06696 (2001-01-01), None
patent: WO 01/63767 (2001-08-01), None
“Analysis of a charge-pump PLL: a new model”; Van Paemel; IEEE Transactions on Communications, vol. 42, Issue 7, Jul. 1994, pp. 2490-2498.
C.R. Hogge, Jr., “A Self Correcting Clock Recovery Circuit”, IEEE Journal of Lightwave Technology, vol. LT-3, No. 6, Dec. 1985.
E. Mullner, “A 20 Gb/s Parallel Phase Detector and Demultiplexer Circuit in a Production Silicon Bipolar Technology with fT=25 GHz”, Proc. IEEE BCTM, pp. 43-45, Oct. 1996.
M. Rau et al., “Clock/Data Recovery PLL Using Half-Frequency Clock”, IEEE Journal of Solid-State Circuits, vol. 32, No. 7, Jul. 1997.
K. Nakamura et al., “A 6 Gb/s CMOS Phase Detecting DEMUX Module Using Half-Frequency Clock”, IEEE 1998 Symposium on VLSI Circuits Digest of Technical Papers.
M. Wurzer et al., “40-Gb/s Integrated Clock and Data Recovery Circuit in a Silicon Biopolar Technology”, IEEE BCTM 8.1, 1998.
Jafar Savoj et al., “A 10-Gb/s CMOS Clock and Data Recovery Circuit”, IEEE 2000 Symposium on VLSI Circuits Digest of Technical Papers.
“Analysis of a charge-pump PLL: a new model”; Van Paemel; IEEE Transactions on Communications, vol. 42, Issue 7, Jul. 1994, pp. 2490-2498.

Affiliated with

Also associated with

Rating

Linear half-rate phase detector and clock and data recovery... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Linear half-rate phase detector and clock and data recovery..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Linear half-rate phase detector and clock and data recovery... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3564260