Optical communications – Transmitter and receiver system – Including synchronization
Reexamination Certificate
2007-03-13
2007-03-13
Payne, David C. (Department: 2613)
Optical communications
Transmitter and receiver system
Including synchronization
C370S217000, C370S218000
Reexamination Certificate
active
10930980
ABSTRACT:
Method and apparatus for recovering a clock and data from a data signal. One method of the invention includes receiving the data signal having a first data rate and receiving a clock signal having a first clock frequency, and alternating between a first level and a second level. The data signal is stored when the clock signal alternates from the first level to the second level, and the stored data signal is provided as a first signal a first amount of time later. The first signal is stored when the clock signal alternates from the first level to the second level, and the stored first signal is provided as a second signal a second amount of time later. A third signal is provided by delaying the first signal for a third amount of time. The third signal is stored when the clock signal alternates from the second level to the first level, and the stored third signal is provided as a fourth signal a fourth amount of time later. A fifth signal is provided by delaying the data signal a fifth amount of time. An error signal is generated by taking the exclusive-OR of the first and fifth signals; and a reference signal is generated by taking the exclusive-OR of the second and fourth signals. The first data rate is equal to the first clock frequency.
REFERENCES:
patent: 4535459 (1985-08-01), Hogge, Jr.
patent: 5301196 (1994-04-01), Ewen et al.
patent: 5619148 (1997-04-01), Guo
patent: 5923455 (1999-07-01), Rokugawa
patent: 6121804 (2000-09-01), Bryan et al.
patent: 6570946 (2003-05-01), Homol et al.
patent: WO 01/06696 (2001-01-01), None
patent: WO 01/63767 (2001-08-01), None
U.S. Appl. No. 09/955,693, filed Sep. 18, 2001, Cao.
Hogge, Jr., “A Self Correcting Clock Recovery Circuit”, IEEE Journal of Lightwave Technology, vol. LT-3, No. 6, Dec. 1985.
Mullner, “A 20 Gb/s Parallel Phase Detector and Demultiplexer Circuit in a Production Silicon Bipolar Technology with fT=25GHz”, Proc. IEEE BCTM, pp. 43-45, Oct. 1996.
Rau et al., “Clock/Data Recovery PLL Using Half-Frequency Clock”, IEEE Journal of Solid-State Circuits, vol. 32, No. 7, Jul. 1997.
Nakamura et al., “A 6 Gb/s CMOS Phase Detecting DEMUX Module Using Half-Frequency Clock”, IEEE 1998 Symposium on VLSI Circuits Digest of Technical Papers.
Wurzer et al., “40 Gb/s Integrated Clock and Data Recovery Circuit in a Silicon Bipolar Technology”, IEEE BCTM 8.1, 1998.
Savoj et al., “A-10 Gb/s CMOS Clock and Data Recovery Circuit”, IEEE 2000 Symposium on VLSI Circuits Digest of Technical Papers.
Broadcom Corporation
Payne David C.
LandOfFree
Linear full-rate phase detector and clock and data recovery... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Linear full-rate phase detector and clock and data recovery..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Linear full-rate phase detector and clock and data recovery... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3729072