Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Frequency of cyclic current or voltage
Reexamination Certificate
2001-10-11
2003-08-12
Le, N. (Department: 2858)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
Frequency of cyclic current or voltage
Reexamination Certificate
active
06605935
ABSTRACT:
BACKGROUND
The invention relates to fractional-N phase locked loops, more particularly to Sigma-Delta controlled fractional-N phase locked loop modulators used for generating continuous phase modulation, and still more particularly to techniques for eliminating nonlinearities in PLL operation.
Phase locked loops (PLLs) are well known, and are useful for generating oscillating signals in many types of circuits, including but not limited to radio circuitry. In digital communication systems, for example in mobile telephone communications operating under the GSM or DCS systems, PLLs may be employed to effect continuous phase modulation (CPM) of a carrier signal.
FIG. 1
is a block diagram of a conventional integer-divide PLL
100
. A phase (frequency) detector
101
compares the phase of a signal supplied by a reference oscillator
103
with the phase of a feedback signal supplied by a frequency divider
105
. The output of the phase detector, which represents the phase difference between the two input signals, is filtered by a filter
107
. The filtered output is then used to control the frequency of an output signal generated by a voltage controlled oscillator (VCO)
109
. The output signal from the VCO
109
, in addition to being supplied as an output from the PLL, is also supplied as an input to the frequency divider
105
, and is thus the source of the feedback source. The PLL
100
is governed by the following equations:
i
e
=
K
P
(
ϕ
R
-
ϕ
o
N
)
ϕ
o
=
i
e
Z
(
s
)
K
V
s
,
(
1
)
where s, K
p
, Z(s), and K
V
are the complex frequency, phase detector gain, loop-filter trans-impedance, and VCO gain, respectively, and &phgr;
R
, &phgr;
o
, and i
e
, are the reference phase (or frequency as 2&pgr;f=s*&phgr;), the VCO phase, and the phase-detector error current, respectively.
Solving the above equations for &phgr;
o
yields the well-known result that f
o
=N·f
R
, that is, the VCO frequency is an integer multiple of the reference frequency.
Since the loop response time to a change in N (e.g., when a new channel is selected) is proportional to 1/f
R
(i.e., it takes a certain number of reference cycles to settle) and the minimum channel spacing equals f
R
, there are conflicting considerations involved in the choice of reference frequency. That is, it would be desirable to set a low value for f
R
to reduce the minimum channel spacing. However, such a setting would result in a larger loop response time, which is undesirable.
To get around the above restriction on channel spacing, fractional-N PLLs have been devised. By employing a variable-modulus divider, rather than an integer divider, it is possible to achieve more flexible divide ratios. For example, performing three successive divisions by 20 followed by one division by 21 results in an average division factor of (3·20+21)/4=20.25 and a channel spacing of f
R
/4. Due to the repetitive nature of this variable modulus division, however, spurious tones will be generated (here at f
o
±n·f
R
) that will modulate the VCO.
To address these problems, &Sgr;&Dgr; modulators have been employed to shape the spurious response of the fractional-N divider. If one examines a typical &Sgr;&Dgr; noise density distribution, it can be seen that the spurious tone is replaced by a spectrum of spurious tones with most of the spurious energy being pushed out in frequency, well beyond the bandwidth of the PLL, essentially being centered around f
R
/2, where f
r
is the clocking rate of the &Sgr;&Dgr; modulator. A thermal noise floor (e.g., thermal noise attributable to the divider circuitry) is also included. As a result of the shaping performed by the &Sgr;&Dgr; modulator, this spurious energy will have a substantially reduced effect on the output signal from the PLL.
&Sgr;&Dgr;-controlled fractional-N PLLs are often used in radio systems for generating spurious-free local oscillator frequencies and to allow faster frequency jumps. By controlling the divider ratio with a Sigma-Delta modulator, modulation with a constant envelope can be generated. By using these properties of the fractional-N PLL, compact radio architectures for constant envelope systems (e.g., GSM, DCS) can be developed. This also means that the complete radio can be integrated in the same ASIC.
An exemplary embodiment of a &Sgr;&Dgr; fractional-N PLL
200
is depicted in FIG.
2
. The phase detector
201
, reference oscillator
203
, filter
207
and VCO
209
are analogous to those counterpart elements described with respect to
FIG. 1
, and therefore need not be described here in detail. The frequency divider
205
in this case is capable of dividing by any integer modulus in the range N±M, and has two inputs: one for receiving a value for N, and another for receiving a value of M. By appropriately varying the value of M as described above, an effective division modulus of N+&dgr;N can be achieved. A &Sgr;&Dgr; modulator
211
is provided that receives a desired channel value, and generates therefrom appropriate values for N and M. A first-order &Sgr;&Dgr; modulator may be used, but this is not essential; higher-order &Sgr;&Dgr; modulators may be used in alternative embodiments.
The &Sgr;&Dgr; noise will be suppressed by the loop response (i.e., if the loop bandwidth is not too wide), but to avoid spurious tones due to &Sgr;&Dgr;-modulator limit cycles (i.e., a repetitive behavior associated with having a period time that is too short), extra noise (“dither”) is typically added to the &Sgr;&Dgr; noise in order to further randomize the &Sgr;&Dgr; noise. The resultant value is then quantized, which adds its own quantization noise, e
q
(k). The resultant value M, which is generated at the output of the &Sgr;&Dgr; modulator
211
, is supplied to one of the modulus inputs of the frequency divider
205
.
To make the noise shaping possible, the divider modulus should not be chosen to be only the two closest integer factors, but should instead be varied between, for example, N−M, . . . , N+M. This extra modulus range is required if noise is to be pushed out in frequency, away from the VCO carrier; otherwise, the loop filter will not be able to suppress the &Sgr;&Dgr; noise. As a consequence of this extended divider modulus range, the instantaneous phase error will be increased. The &Sgr;&Dgr;-loop equations then become:
i
e
=
K
P
(
ϕ
R
-
ϕ
o
N
+
δ
N
+
N
Δ
Σ
)
ϕ
o
=
i
e
Z
(
s
)
K
V
s
,
(
2
)
where N+&dgr;N and N
&Sgr;&Dgr;
represent the fractional division ratio and the &Sgr;&Dgr;-modulator noise, respectively.
FIG. 3
is a block diagram of a typical embodiment of the conventional phase detector
201
. The use of first and second digital latches
301
,
303
enables multiple states (not shown in
FIG. 3
) and, hence, an extended range of the phase detector
201
. In operation, the first latch
301
controls whether a first charge pump
305
is on or off. Similarly, the second latch
303
controls whether the second charge pump
307
is on or off. The first and second charge pumps
305
,
307
are connected in series, with the phase detector output current, I
out
, being supplied at the connection point between the two charge pumps. The amount of phase detector output current, I
out
, is related to whether none, one, or both of the first and second charge pumps
305
,
307
are turned on. The amount of time that I
out
is non-zero is a function of the phase difference between the first and second input signals, f
ref
and prescaler (Presc.). (The prescaler signal may also be referred to as a “feedback signal”, when the phase detector
201
is used in a PLL.) Each of these signals is supplied to a clock input of a respective one of the first and second latches
301
,
303
. The first of these signals to present a clocking edge causes the output of the corresponding latch to be asserted, which in turn, causes a corresponding one of the first and secon
Burns Doane Swecker & Mathis L.L.P.
Lair Donald M
Le N.
Telefonaktiebolaget L M Ericsson (PUBL)
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