Linear digital phase lock loop

Pulse or digital communications – Spread spectrum – Direct sequence

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Details

331 1A, 328 63, H03K 100

Patent

active

042107768

ABSTRACT:
A linear digital phase locked-loop generates a recovered clock which is synchronized with level transitions in the data signal being tracted. Internally generated clock pulses are cyclically counted to generate a binary ramp signal. This ramp signal is added to another digital signal whose value depends upon the phase and frequency departure of the data signal from the recovered clock. A first order linear accumulator supplies a modified summation signal upon transistions in the data signal and the recovered clock is adjusted to fall in sync with the data. A second order loop may be selectively employed for phase and frequency tracking. The second order loop includes a further linear accumulator which supplies a digital signal to be combined with the binary ramp signal to adjust the recovered clock frequency until the first and second order loops are stablished, at which time the clock is synchronized with the data. As the first and second order loops stabilize, the composite behavior is linear and may be described by classical second order servo-control loop equations. This allows for linear analysis of systems using this bit synchronizer as a system component.

REFERENCES:
patent: 3564425 (1971-02-01), Brok
patent: 3646452 (1972-02-01), Horowitz et al.
patent: 3889186 (1975-06-01), Larson

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