Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
2000-02-02
2002-03-19
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S753000, C438S756000
Reexamination Certificate
active
06358860
ABSTRACT:
TECHNICAL FIELD
The present invention relates to calibration of line width measuring instruments, and in particular to manufacture of a calibration standard containing line surface features thereon of a certified width. The invention further relates to calibration standards useful for determining the profile or shape of a line width measuring instrument's probe tip.
BACKGROUND ART
As integrated circuit features continue to shrink from 0.25 &mgr;m to 0.18 &mgr;m line widths and smaller, it has become ever more important that such feature dimensions can be measured precisely and accurately. As the feature sizes drop below the resolution limit for optical measuring techniques, more direct physical measurement, e.g. with a scanable probe tip, and in particular, atomic force microscopy, becomes the favored method. Atomic force microscopes (AFMs) are very precise, with excellent repeatability (when using the same machine and probe); but, without a way to calibrate these instruments, at the low end of their measurement range, they tend to be inaccurate, with different AFM instruments (or even the same instrument with different probe tips) yielding different results.
Line width calibration standards do exist, with the best standards available to date having a certifiable line width of greater than 0.7 &mgr;m. Thinner lines (0.25 &mgr;m and less) are desired, but production of such standards (especially those 0.10 &mgr;m or thinner) are impeded by resolution limits of the best available lithographic techniques and by the need to accurately measure the lines produced in order to certify the standard itself. Present line width standards typically depend on pitch and/or duty cycle measurements of a number of closely spaced lines on the standard to reach a 3 &mgr;m, 1.8 &mgr;m or the best 0.7 &mgr;m certified width, since it is much easier to accurately measure line plus spacings than the line width itself. Standards with isolated lines (with separations much larger than the probe tip dimensions) are desired, but at submicron dimensions it is generally understood that precise measurement of isolated lines would have to be made using an atomic force microscope or other probe-based instrument, the same type of measurement instrument that requires such a calibration standard in the first place. Traceability of a measurement standard is very important to guarantee accuracy. Traceability establishes a chain of reference back to an already recognized standard, whether of a national or international authority, or well established scientific first principles. In the case of isolated line widths, no such traceable standard yet exists.
Accordingly, it may be advantageous to provide a method of making certified submicron isolated line width standards for calibration of line width measuring instruments.
In addition, it may be advantageous to provide a method of certifying a submicron isolated line width standard that does not rely on probe-based direct physical measurement of the line width for its certification.
Furthermore, it may be advantageous to provide a calibration standard for probe-based instruments that is useful for determining the profile or shape of a line width measuring instrument's probe tip.
SUMMARY OF THE INVENTION
In an embodiment, a method of making and certifying a line width standard may include thermally growing a silicon dioxide film layer on a top surface and vertical side walls of one or more silicon strips or mounds formed over a silicon dioxide layer on a silicon substrate, optically measuring the thickness of the film layer on the top surface of the strip(s), removing the film layer from the top surface of the strip(s) without removing any of the film layer from the side walls, and removing at least some of the silicon of the strip(s) using an etchant that is highly selective of silicon relative to silicon dioxide, thereby leaving the silicon dioxide film layer from the side walls as two or more isolated silicon dioxide lines. The determination of the width of such silicon dioxide lines depends on knowing the ratio of the thicknesses of the film layer on the top and side wall surfaces of the silicon strips or mounds. This can be accurately found by testing samples made by the same process, e.g. by cross-section scanning electron microscopy of cut up test pieces. Note that only the ratio of these thicknesses is needed from the test samples, not the thicknesses themselves. Then, by optically measuring (e.g., by spectroscopic ellipsometry) the thickness of the film layer on the top surface of the standard being manufactured prior to its being subsequently removed, the side wall thickness can be calculated. This side wall thickness equals the line width of the finished standard.
In a second embodiment, if silicon top surface is chosen to be the [100] crystal plane, then the silicon strips or mounds can have sloping rather than vertical side walls. The silicon dioxide film layer can be grown as in the first embodiment, the top surface film selectively removed, and a portion of the silicon material also removed. This will leave isolated upward projecting, but tilted, silicon dioxide blade or fin-like members. The upper blade edge of these fin-like members forms a well-defined surface feature over which an atomic force microscope probe tip may pass to produce a probe signal representing the shape of the probe tip. This allows the probe tip shape to be characterized and taken into account when passing over surface features of unknown characterization.
In either embodiment, the oxide features may not only form parallel pairs of isolated extended lines but can also assume other linear shapes, such as square, rectangular, parallelogram or octagonal perimeter features to permit calibration or probe characterization in two or more orthogonal or diagonal directions, as needed by the particular system being calibrated using the standard. Multiple features may be arranged on the surface of the standard in an array or grid, concentrically, or in any other convenient layout.
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Laird Ellen R.
Scheer Bradley W.
Chen Kin-Chan
Conley & Rose & Tayon P.C.
Meyertons Eric B.
Utech Benjamin L.
VLSI Standards, Inc.
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