Line synchronization detection circuit

Details Line synchronization detection circuit Line synchronization detection circuit

1989-02-17

1990-07-31

Shepperd, John W.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358153, 358148, H04N 512, H04N 510

Patent

active

049454137

ABSTRACT:
A detection circuit of a line synchronization signal in a video signal wherein the synchronization signal is sent to a phase locked loop (PLL) comprises a voltage controlled oscillator (8), for supplying a line scanning signal to a display. The following steps are provided: inhibiting the operation of the loop and setting the VCO to its free frequency, in the absence of the line synchronization signal; supplying a detection window in relation with the oscillations of the VCO; and detecting the presence of the synchronization signal in this window for supplying either an enabling signal after the detection of a determined number of synchronization tops, this enabling signal connecting again the VCO in the loop, or an inhibiting signal if the detection is interrupted during the determined number of synchronization tops.

REFERENCES:
patent: 4203076 (1980-05-01), Yamashita
patent: 4467359 (1984-08-01), Hosoya
patent: 4498103 (1985-02-01), Aschwanden
patent: 4520393 (1985-05-01), Zwijsen et al.
patent: 4535359 (1985-08-01), Duijkers
patent: 4769704 (1988-09-01), Hirai et al.
patent: 4809068 (1989-02-01), Nagai
"Deflection Processor Eliminating TV Hold Controls"; by Andy Hennigan; Electronic Engineering; May 1984; pp. 77-80.

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