Line power failure scheme for a gaming device

Details Line power failure scheme for a gaming device Line power failure scheme for a gaming device

1986-08-05

1988-11-01

Moffitt, James W.

Static information storage and retrieval

Powering

Data preservation

273138, 364900, 371 66, G11C 800, G06F 1100, H03M 1300, A63B 700

Patent

active

047824689

ABSTRACT:
A power failure scheme for a gaming device in which, upon the detection of a failure of the line power, particular processing operations are completed before power is completely lost. A regulated D.C. power supply coupled to the line power generates an interrupt having the highest priority upon detecting a failure of the line power. The main processor of the gaming device is responsive to a power fail interrupt to complete any access to a safe memory which may have been on-going at the time the interrupt was generated or to complete any state transition which was on-going at the time the interrupt was generated.

REFERENCES:
patent: 4285240 (1981-08-01), Gold
patent: 4535409 (1985-08-01), Jindrick et al.
patent: 4582324 (1986-04-01), Koza et al.
patent: 4652998 (1987-03-01), Koza et al.
patent: 4660833 (1987-04-01), Dickinson et al.

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