Line interface integrated circuit and packet switch

Details Line interface integrated circuit and packet switch Line interface integrated circuit and packet switch

2000-10-24

2004-08-31

Chin, Wellington (Department: 2664)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S412000, C370S413000

Reexamination Certificate

active

06785290

ABSTRACT:

RELATED APPLICATION
This application claims the benefit of priority under 35 U.S.C. §119 of Japanese Patent Application No. H11-302056, filed on Oct. 25, 1999, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a line interface integrated circuit and a packet switch, and more particularly, to a line interface circuit capable of efficiently inserting or extracting packets, and a packet switch using such a line interface integrated circuit.
2. Description of the Related Background Art
There is an ATM (asynchronous transfer mode) communication network as one of currently widespread communication networks of fixed length packets. ATM networks are used to exchange not only ordinary data cells but also non-data cells for maintenance and management of the ATM networks.
For example, ATM networks can use OAM (operation and maintenance) cells for the purpose of maintenance of the networks. Furthermore, RM (resource management) cells can be also used for the purpose of efficiently using network resources of the ATM networks.
In order to operate and manage an ATM network by using those OAM cells and RM cells, communication terminals or ATM switches are required to insert OAM cells and RM cells into a flow of ordinary data cells or extract OAM cells and RM cells from the flow of ordinary cells. A configuration of an ATM switch of this type is shown in FIG.
9
.
As shown in
FIG. 9
, the ATM switch has physical layer controllers
110
(
1
) through
110
(N), line interfaces
112
(
1
) through
112
(N), routing switch
114
, line interfaces
116
(
1
) through
116
(N), and physical layer controllers
118
(
1
) through
118
(N).
The line interfaces
112
(
1
) through
112
(N) and the physical layer controllers
110
(
1
) through
110
(N) are associated with respective input ports. That is, in the example of
FIG. 9
, there are N input ports. The line interfaces
116
(
1
) through
116
(N) and the physical layer controllers
118
(
1
) through
118
(N) are associated with respective output ports. That is, in the example of
FIG. 9
, there are N output ports.
The physical layer controllers
110
(
1
) to
110
(N) are connected to physical layers, respectively, and supplied with frame-formatted transmission data from the physical layers. As to these frame-formatted transmission data inputted into physical layer controllers
110
(
1
) to
110
(N), ATM cells are extracted from each frame-formatted transmission data and outputted to the line interfaces
112
(
1
) to
112
(N). That is, a plurality of ATM cells are stored in one frame.
The line interfaces
112
(
1
) to
112
(N) connected between the physical layer controllers
110
(
1
) to
110
(N) and the routing switch
114
function to add information required for routing the ATM cells in the routing switch
114
to ATM cells, rewrite headers of ATM cells, and so on. The line interfaces
112
(
1
) to
112
(N) also function to temporarily store ATM cells to be outputted to the routing switch
114
and output them to the routing switch
114
, depending upon the processing status of the routing switch
114
. The line interfaces
112
(
1
) to
112
(N) are concerned in processing ATM cells from the physical layer controllers
110
(
1
) to
110
(N) toward the routing switch
114
, and the part of the ATM switch where these ATM cells enter into the routing switch
114
is hereinafter called the ingress side.
ATM cells outputted from the line interfaces
112
(
1
) to
112
(N) are inputted to the routing switch
114
. By switching function of the routing switch
114
based on header information of the ATM cells, these ATM cells are outputted to a corresponding one of line interfaces
116
(
1
) to
116
(N), respectively.
The line interfaces
116
(
1
) to
116
(N) temporarily store ATM cells inputted from the routing switch
114
and sequentially output them to the physical layer controllers
118
(
1
) to
118
(N) as soon as the output port is unoccupied. The line interfaces
116
(
1
) to
116
(N) are concerned in processing ATM cells from the routing switch
114
toward the physical layer controllers
118
(
1
) to
118
(N), and the part of the ATM switch where these ATM cells are outputted from the routing switch
114
is hereinafter called the egress side.
Based on ATM cells inputted into the physical layer controllers
118
(
1
) through
118
(N), frame-formatted transmission data are generated in the physical layer controllers
118
(
1
) to
118
(N), and the transmission data is outputted from a physical layer.
In case of an ATM switch having configuration as shown in
FIG. 9
, insertion and extraction of the OAM cells or the RM cells are often conducted in the ingress-side line interfaces
112
(
1
) to
112
(N) and/or egress-side line interfaces
116
(
1
) to
116
(N). Configuration of line interfaces
112
(
1
) to
112
(N) having such functions of inserting and extracting of the OAM cells and the RM cells is shown in FIG.
10
.
FIG. 10
illustrates configuration of an ingress-side line interface
112
(
1
) as an example.
With reference to
FIG. 10
, explanation is made below about the process of ordinary data cells passing through the conventional line interface
112
(
1
).
ATM cells inputted from the physical layer controller
110
(
1
) are classified in a physical layer interface
130
. Based on the classification, class information CI is notified from the physical layer interface
130
to a scheduler
132
. The class information CI indicates an identification number of a queue formed in a cell buffer
134
. The scheduler
132
manages the queues, each of which corresponds to the class.
The scheduler
132
in receipt of the class information CI outputs a write request W to write ATM cells to the cell buffer
134
. Responsively, ATM cells are stored in the cell buffer
134
via a cell storage controller
131
. The scheduler
132
writes data of a single ATM cell in the cell buffer
134
, and thereafter adds one entry in a class queue the ATM cell belongs to, and increases the length of the queue by one. Herein below, let it called “enqueue” to write data of an ATM cell in the cell buffer
134
and increase the length of a queue the ATM cell belongs to.
The scheduler
132
selects any queue or queues equal to or longer than 1 from a plurality of queues provided for individual classes, and selects only one to be outputted with the highest priority. The scheduler
132
extracts the forefront one entry of the selected queue, and a data read request to read data of the ATM cell that entry belongs to. Herein below, let it called “dequeue” to read out cell data from the cell buffer
134
and decrease the length of the queue the ATM cell belongs to.
Next referring to
FIG. 10
, explanation is made about operations in the line interface
112
(
1
) for extracting an OAM cell and RM cell, and operations therein for inserting an OAM cell and RM cell.
The physical layer interface
130
manages information for individual lines, such as line qualities (class information CI), cell passing frequencies, etc. When the physical layer interface
130
decides on the basis of contents of input cells and line information that an ATM cell inputted is addressed to the host CPU, it writes the data of the ATM cell in a FIFO memory
136
prepared separately, instead of the cell buffer
134
.
The FIFO memory
136
is capable of storing a plurality of ATM cell data. The host CPU
150
connected to the line interface
112
(
1
) has the function of sequentially reading out ATM cell data from the FIFO memory
136
into temporary RAM
138
, the function of delivering information obtained therefrom to application software, and other functions.
On the other hand, for inserting an OAM cell or RM cell, the host CPU
150
first writes data of the ATM cell to be inserted in the temporary RAM
138
, and requests a cell insertion controller
140
to next insert the ATM cell. The cell insertion controller
140
outputs ATM cells stored in the temporary RAM
138
through a selector
142
to a switch int

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