Multiplex communications – Wide area network – Packet switching
Patent
1994-05-02
1996-07-02
Kizou, Hassan
Multiplex communications
Wide area network
Packet switching
370 82, 370 942, 370 99, 3701051, 3701101, 375376, H04L 1256
Patent
active
055330177
ABSTRACT:
Exchangeable LID modules are provided to enable the frame relay switching system to be interfaced to a specific data terminal, for example, synchronous, asynchronous terminals or T1 line, by performing on the receive side the physical translation of information on the input lines to clock signal CLK and HDLC framed data. On the transmit side, the HDLC framed data and clock signal CLK are translated into the data appropriate for a data terminal. The type of the translation is specific to the line to be interfaced with. To support a synchronous data terminal, a synchronous receiver is provided that extracts valid data patterns from a synchronous data stream. The data patterns are replaced with the data stream of appropriate levels when data are transmitted. When data are received from a T1 line, the LID splits the received data stream into user data and signalling data. The signalling data are buffered to form a signalling frame sent to a signalling frame relay packet management device (FRYPAM) separate from a user data FRYPAM that receives user data frames. To support an asynchronous data terminal, a microprocessor is provided to handle PAD and LAPB operations for transforming asynchronous data into X.25 format.
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patent: 5115208 (1992-05-01), Masdea et al.
patent: 5251207 (1993-10-01), Abensour et al.
patent: 5315588 (1994-05-01), Koyiwara et al.
Advanced Micro Devices , Inc.
Kizou Hassan
Rao Seema
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