Line equalizer operable in response to an input signal of a vari

Details Line equalizer operable in response to an input signal of a vari Line equalizer operable in response to an input signal of a vari

1985-09-04

1987-08-11

Griffin, Robert L.

Pulse or digital communications

Repeaters

Testing

333 18, 364724, H03K 5159

Patent

active

046866868

ABSTRACT:
In a line equalizer responsive to an input signal of a variable data rate for producing an equalizer output signal, a control circuit (12) supplies an equalizer circuit (11) with a selection signal (SEL) which is determined by the data rate and an output level of the equalizer output signal to select a frequency-gain characteristic that is matched with the line loss characteristic of a line. The equalizer circuit is implemented by a switched capacitor circuit and samples the input signal via a clock signal (CK) a clock frequency of which is varied by a clock signal controller (51) in consideration of the data rate. An additional equalizer circuit may be connected in cascade to the equalizer circuit and controlled by an additional control signal determined by the data rate and the output level. In this event, the selection signal may be determined only by the output level with the clock signal left out of consideration.

REFERENCES:
patent: 4365338 (1980-12-01), McRae et al.
patent: 4453143 (1984-06-01), Bennett
patent: 4459698 (1984-07-01), Yumoto et al.
patent: 4555788 (1955-11-01), Merrill

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