Electricity: power supply or regulation systems – Self-regulating – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2000-01-31
2001-01-23
Wong, Peter S. (Department: 2838)
Electricity: power supply or regulation systems
Self-regulating
Using a three or more terminal semiconductive device as the...
Reexamination Certificate
active
06177789
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to line drivers and, more particularly, to a line driver for producing operating condition invariant signal levels.
2. Description of the Related Art
A line driver is a device that drives a signal onto a transmission line, such as a local-area-network. Line drivers are typically associated with a specific network standard, such as the 100BASE-T standard (IEEE 100-Mbit/sec unshielded twisted-pair (UTP) 802.3), which defines the signaling rate, the signaling scheme, and the type of wiring of the network. One signaling protocol that is used with 100BASE-T-based networks is the MLT-3 (tri-level) signaling protocol which defines a 2Vpp signal that is output at 125 Mbits per second.
FIG. 1
shows a schematic diagram that illustrates a conventional 100BASE-T MLT-3 line driver
100
. As shown in
FIG. 1
, driver
100
includes a transmit circuit
110
which has a pair of differential outputs OUT+ and OUT−, and a transformer
112
which has a pair of inputs IN+ and IN− that are connected to the outputs OUT+ and OUT−. In addition, transformer
112
also has a pair of transmission outputs TX+ and TX− that are connected to a transmission line
114
, such as a 100-ohm line. Further, transformer
112
has a center tap connected to a power supply voltage Vcc.
As additionally shown in
FIG. 1
, circuit
100
includes a first resistor R
1
which is connected between the power supply voltage Vcc and the output OUT+, and a second resistor R
2
which is connected between the power supply voltage Vcc and the output OUT−. Resistors R
1
and R
2
each have a resistance that is equal to one-half the impedance of the transmission line, i.e. 50 ohms.
FIG. 2
shows a schematic diagram that illustrates a conventional transmit circuit
200
. As shown in
FIG. 2
, circuit
200
, which represents a first example of an implementation of circuit
110
, includes a first transistor Q
1
which has a drain connected to the output OUT+, a gate connected to receive a first signal SS
1
, and a source. Further, circuit
200
also includes a second transistor Q
2
which has a drain connected to the output OUT−, a gate connected to receive a second signal SS
2
, and a source.
In addition, circuit
200
further includes a current source
210
which is connected between transistors Q
1
and Q
2
, and ground. Current source
210
, in turn, includes a tail current transistor Q
3
which has a drain connected to the sources of transistors Q
1
and Q
2
, a gate, and a source connected to ground.
Current source
210
also includes a mirroring transistor Q
4
which has a drain, a gate connected to the gate of transistor Q
3
and the drain of transistor Q
4
, and a source connected to ground. Transistor Q
3
is formed to be A times larger than transistor Q
4
. Further, a bandgap current source BG outputs a compensated current to transistors Q
3
and Q
4
that defines the gate-to-source voltages of transistors Q
3
and Q
4
. Since the gate-to-source voltages are defined by a compensated current, the gate-to-source voltages are substantially independent of variations in the power supply voltage Vcc.
FIGS.
3
A-
3
E are timing diagrams that illustrate the operation of driver
100
of
FIG. 1
when utilizing transmit circuit
200
of FIGS.
2
and the MLT-3 signaling protocol. The MLT-3 signaling protocol defines three signal levels which correspond to three of the logic states defined by the first and second signals SS
1
and SS
2
.
As shown in FIGS.
3
A-
3
D, the first signal level occurs when the signal SS
1
has a logic low and the signal SS
2
has a logic high such that transistor Q
1
is turned off and transistor Q
2
is turned on. Under these conditions, current source
210
pulls a current I through resistor R
2
which sets up a voltage on input IN− that is less than the power supply voltage Vcc. (The voltage on input IN− is less than the power supply voltage Vcc since the voltage is equal to the power supply voltage Vcc less the voltage drop across resistor R
2
.)
At the same time, the action of transformer
112
causes a complementary voltage, which is greater than the power supply voltage Vcc, to appear on the input IN+. The voltage on input IN+ is greater than the power supply voltage Vcc by the same magnitude that the voltage on input IN− is less than the power supply voltage Vcc. Thus, a positive voltage is applied across the inputs IN+ and IN−.
The second signal level occurs when the signal SS
1
has a logic high and the signal SS
2
has a logic low such that transistor Q
1
is turned on and transistor Q
2
is turned off. Unlike the previous example, current source
210
now pulls the current I through resistor R
1
which sets up a voltage on input IN+ which is less than the power supply voltage Vcc. (As in the previous example, the voltage on input IN+ is less than the power supply voltage Vcc since the voltage is equal to the power supply voltage Vcc less the voltage drop across resistor R
1
.)
At the same time, the action of transformer
112
causes a complementary voltage, which is greater than the power supply voltage Vcc, to appear on the input IN−. (As above, the voltage on input IN− is greater than the power supply voltage Vcc by the same magnitude that the voltage on input IN+ is less than the power supply voltage Vcc.) Thus, a negative voltage, which has a polarity opposite to the polarity of the positive voltage, is applied across the inputs IN+ and IN−.
The third signal level occurs when the signals SS
1
and SS
2
both have logic highs such that transistors Q
1
and Q
2
are both turned on. In this case, current source
210
pulls one-half of the current I through both resistors R
1
and R
2
which sets up substantially equivalent voltages on inputs IN+ and IN−. The action of transformer
112
, in turn, forces the voltages on inputs IN+ and IN−to both be substantially equal to the power supply voltage Vcc.
In addition, as shown in
FIG. 3E
, a voltage COM at the drain of tail current transistor Q
3
varies as transistors Q
1
and Q
2
are turned on and off. The variation results from the difference in resistance provided by transistor Q
1
when transistor Q
1
sinks all of current I, and when transistor Q
1
sinks only one-half of current I. The variation also results from the difference in resistance provided by transistor Q
2
when transistor Q
2
sinks all of current I, and when transistor Q
2
sinks only one-half of current I.
One of the disadvantages of transmit circuit
200
is that transistor Q
3
does not have a high enough output impedance. A lower output impedance means that variations in the power supply voltage Vcc lead to variations in the steady state peak-to-peak differential voltage (V
OD
) of transmit signals TX+ and TX−.
Although the gate-to-source voltages of transistors Q
3
and Q
4
are substantially independent of variations in the power supply voltage Vcc, the voltage on the drain of transistor Q
3
is not independent of the power supply voltage Vcc. For example, when the first signal level occurs, the signal SS
1
has a logic low and the signal SS
2
has a logic high, which is equal to the power supply voltage Vcc. As a result, the voltage on the drain of transistor Q
3
is equal to the power supply voltage Vcc less the gate-to-source voltage of transistor Q
2
, i.e., Vcc−V
GS
Q
2
. Thus, variations in the power supply voltage Vcc cause variations in the drain voltage of transistor Q
3
.
When the variations in the drain voltage of transistor Q
3
are combined with the low output impedance of transistor Q
3
, variations in the drain voltage of transistor Q
3
lead to variations in the current I. Variations in the current I lead to variations in the voltages at outputs OUT+ and OUT− which, in turn, cause the voltages of the transmit signals TX+ and TX− to also vary. Thus, variations in the power sup
Ceekala Vijaya
Mohan Jitendra
Varadarajan Devnath
Laxton Gary L.
Limbach & Limbach L.L.P.
National Semiconductor Corporation
Wong Peter S.
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