Line driver circuit for a semiconductor memory device

Details Line driver circuit for a semiconductor memory device Line driver circuit for a semiconductor memory device

2005-09-21

2008-03-18

Yoha, Connie C. (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230070, C365S149000, C365S185230

Reexamination Certificate

active

07345945

ABSTRACT:
A semiconductor memory device having a word line driver circuit configured in stages. A plurality of sub word line driver circuits are connected, in parallel, to each main word line, and provide a sub word line enable signal to a selected sub word line in response to a main word line enable signal provided through a main word line. A plurality of (local) word line driver circuits are connected in parallel, to each sub word line and provide a local word line enable signal to a selected local word line in response to the (main/sub) word line enable signal so as to operate a plurality of memory cells connected to the selected local word line. The transistor count and layout area of a semiconductor memory device decreases and a reduced chip area can be achieved.

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