Limiting loss in a circuit

Details Limiting loss in a circuit Limiting loss in a circuit

2002-06-14

2003-04-15

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Compensating for or preventing signal deterioration

C377S073000, C377S074000, C327S173000, C327S176000, C327S331000

Reexamination Certificate

active

06549605

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to integrated circuits. More particularly, the invention is related to avoidance of loss in integrated circuits.
BACKGROUND
In certain applications, it is desirable to limit the amount of time a signal is active in MOS (complementary metal oxide semiconductor) circuits to protect the circuits against various circuit failure modes. One example of a circuit failure mode is a dynamic decay due to subthreshold leakage. A shift register circuit
10
is shown in
FIG. 1
to illustrate the deleterious effects of subthreshold leakage.
The shift register circuit
10
is shown with only three stages for ease of understanding. Each stage comprises a pass gate (or dynamic latch)
15
, a dynamic storage node
35
,
55
or a static storage node
45
, and an inverter
20
formed by a PFET (P-channel field effect transistor) and an NFET (N-channel field effect transistor). A shift signal
27
and its inverse
29
, formed by an inverter
28
, are connected to each passgate
15
. The passgates
15
have alternating PFET/NFET connections to the control lines (signal
27
and its inverse
29
). Thus, the first passgate
15
has a PFET hooked to the shift signal
27
, the second passgate
15
has an NFET hooked to the shift signal
27
, and so on.
The passgates
15
store the logic values at the storage nodes
35
,
45
, and
55
, which are buffered through the inverters
20
to nodes
30
,
40
and
50
, respectively. When the shift signal
27
transitions from low to high (its inverse
29
transitions from high to low), the first and third passgates
15
“turn off,” preventing the new values on nodes
30
and
50
from transferring to storage nodes
35
and
55
, respectively. At the same time, the second (and other even) passgate(s) turn on. As a result, the logic value at the node
40
passes to node
45
. The first and third passgate
15
being “off” ensures that the correct value is held for storage node
45
.
In this design, the logic states stored by the passgates
15
are shifted right each time the inverse shift input signal
29
pulses high.
However, subthreshold leakage occurs through the FETs forming the passgates
15
. As used herein, subthreshold leakage is current from source to drain when the gate is off (Vgs=−Vdd for a PFET, Vgs=0 for an NFET).
A PFET conducts from source to drain or “turns on” when its gate voltage is low with respect to its source; whereas an NFET turns on when its gate voltage is high with respect to its source. For example, if the shift signal
27
remains high long enough while node
30
is low and node
35
is high, the subthreshold leakage can result in the loss of the stored charge on node
35
through leakage through the first passgate
15
's NFET into ground (through node
30
). Protecting the dynamic storage nodes
35
and
55
from failure due to subthreshold leakage requires careful control of the timing of the shift signal
27
. However, given the magnitude of variations present in CMOS circuit manufacturing, a one-size-fits-all solution is not practical.
One approach to compensate for subthreshold leakage is to use a leakage limiting circuit connected to the shift register circuit
10
. The leakage limiting circuit may track leakage and truncate pulses of the input shift signal
27
when NFET or PFET leakage occur to a predetermined extent, as described in U.S. Pat. No. 6,292,041, incorporated by reference in its entirety herein.
However, for very low leakage process conditions, the time needed to trip the leakage limiting circuit may be very long. The longer circuit tripping time may result in unwanted behavior due to very long slew rates on the output of the circuit.
SUMMARY
A circuit for limiting loss in a second circuit is described. The circuit may include a first timer, a second timer and one or more logic gates. The first timer may produce a first output in a given state if the duration of a pulse for use with the second circuit reaches a first predetermined amount of time, where the first predetermined amount of time is related to a parameter of the second circuit. The second timer may produce a second output in the given state if the first timer does not produce the first output in the given state when the duration of the pulse reaches a second predetermined amount of time. The one or more logic gates may have an output that is the same as the pulse unless and until the output of the first timer or the second timer is in the given state, at which time, the output of the one or more logic gates is forced to a non-pulsed state.


REFERENCES:
patent: 6292041 (2001-09-01), Naffziger

Affiliated with

Also associated with

Rating

Limiting loss in a circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Limiting loss in a circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Limiting loss in a circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3025972