Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Reexamination Certificate
2011-06-21
2011-06-21
Kim, Kenneth S (Department: 2111)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
C711S140000, C711S146000, C712S023000, C712S225000, C712S029000, C712S029000
Reexamination Certificate
active
07966478
ABSTRACT:
A method for reducing entries searched in a load reorder queue (LRQ) when snoop instructions are executed by a processor, including checking load reorder queue (LRQ) entries located between a load_peril_snoop register and a lrq_tail register for addresses matching the address of the snoop; and setting a snooped bit in the LRQ entry for any matches found.
REFERENCES:
patent: 5737636 (1998-04-01), Caffo et al.
patent: 5745729 (1998-04-01), Greenley et al.
patent: 6148394 (2000-11-01), Tung et al.
patent: 6266768 (2001-07-01), Frederick, Jr. et al.
patent: 7302527 (2007-11-01), Barrick et al.
Altman Erik R.
Srinivasan Vijayalakshmi
Cantor & Colburn LLP
International Business Machines - Corporation
Kim Kenneth S
Percello Louis J.
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