Limiting entries in load issued premature part of load...

Details Limiting entries in load issued premature part of load... Limiting entries in load issued premature part of load...

2011-06-28

2011-06-28

Kim, Kenneth S (Department: 2111)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

C711S140000, C711S146000, C712S225000, C712S029000, C712S029000

Reexamination Certificate

active

07971033

ABSTRACT:
A method for reducing the number of load instructions in the load reorder queue (LRQ) that are searched when a load instruction is executed by a processor, including dispatching the load instructions; inserting the load instructions in the LRQ in program order; clearing a load received data field; executing the load instructions; checking load reorder queue (LRQ) entries; re-executing the load instruction of the matching LRQ entry; continuing execution; getting the load data; setting the load received data field; comparing a load sequence number (LSQN) of each load instruction to a snoop_safe register contents; ANDing all the load received data bits if the LSQN is greater in magnitude to the snoop_safe; setting the snoop_safe register to the LSQN of the load instruction; searching the LRQ entry; and setting a load_peril_snoop register to the LRQ index value where the first load instruction younger to the snoop_safe was found.

REFERENCES:
patent: 5737636 (1998-04-01), Caffo et al.
patent: 5745729 (1998-04-01), Greenley et al.
patent: 5751983 (1998-05-01), Abramson et al.
patent: 6266768 (2001-07-01), Frederick, Jr. et al.
patent: 7302527 (2007-11-01), Barrick et al.

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