Limited output address register technique providing...

Details Limited output address register technique providing... Limited output address register technique providing...

2006-06-13

2006-06-13

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S233100

Reexamination Certificate

active

07061823

ABSTRACT:
A limited output address register technique for selectively variable write latency in double data rate 2 (DDR2) integrated circuit memory devices providing a reduced number of paths directly connected to the output. A chain of DQ flip-flops is disclosed which is only loaded on valid write address commands but shifts continually thereafter every clock cycle. Since new READ or WRITE commands cannot be issued on successive cycles, at any given point in the chain an address (or state) is valid for at least two cycles. Therefore, a selected point in the register chain can be used to satisfy the requirements for two different latencies. For DDR2, having N write latency cases, only ceil(N/2) access points to the write address output have to be provided thereby saving on-chip area and increasing speed. In a specific embodiment disclosed, DDR1 may also be supported.

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patent: 2005/0138456 (2005-06-01), Song
patent: 2004-253123 (2004-09-01), None
Jedec Standard, DDR2 SDRAM Specification, JESD79-2A, JEDEC Solid State Technology Association, Jan. 2004, pp. i-viii, 1-75.
Davis, Brian, Mudge, Trevor, Jacob, Bruce, Cuppu, Vinodh, DDR2 and Low Latency Variants, Electrical Engineering & Computer Science, University of Michigan, Electrical & Computer Engineering, University of Maryland, pp. 1-15.

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