Limit equalizer output based timing loop

Details Limit equalizer output based timing loop Limit equalizer output based timing loop

2008-01-24

2010-11-02

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Phase or time of phase change

C341S155000, C375S355000

Reexamination Certificate

active

07825836

ABSTRACT:
A timing loop for generating a channel clock signal for driving an analog to digital converter (ADC) includes a slicer bias loop configured to generate an asymmetry compensation signal for a digital output signal from the ADC, the first adder configured to asymmetrically compensate the digital output signal based on the asymmetry compensation signal from the slicer bias loop, a limit equalizer configured to limit a boost range of the asymmetrically compensated digital output signal from the adder, a slicer configured to generate a temporary decision signal based on the asymmetrically compensated digital output signal from the limit equalizer, a phase detector configured to generate a timing error signal based on the asymmetrically compensated digital output signal from the limit equalizer and the temporary decision signal from the slicer; and the first filter configured to generate a clock signal for driving the ADC based on the time error signal from the phase detector.

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